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ORCIDAjith Amerasekera
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2010 – 2019
- 2016
[c10]Hyeon-Min Bae, Ajith Amerasekera:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links. ISSCC 2016: 54-55- 2015
- [c9]Gerrit den Besten, Ajith Amerasekera:
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee. ISSCC 2015: 174-175 - 2014
- [j3]Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems. IEEE J. Solid State Circuits 49(1): 202-211 (2014) - [c8]Leland Chang, Ajith Amerasekera, Takashi Hashimoto:
ES2: Data centers to support tomorrow's cloud. ISSCC 2014: 523 - 2013
- [c7]Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan:
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems. ISSCC 2013: 192-193 - [c6]Nicola Da Dalt, Ajith Amerasekera:
ES3: High-speed communications on 4 wheels: What's in your next car? ISSCC 2013: 515 - 2012
- [c5]Ajith Amerasekera, Makoto Nagata
:
Foreword. VLSIC 2012: 1-2 - [e1]Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera:
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, ISBN 978-1-4503-1249-3 [contents] - 2010
- [c4]Ajith Amerasekera:
Ultra low power electronics in the next decade. ISLPED 2010: 237-238
2000 – 2009
- 2008
- [j2]Ajith Amerasekera:
The Changing Design Landscape. IEEE Des. Test Comput. 25(4): 333 (2008) - 2007
- [c3]Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth:
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. ISSCC 2007: 436-591 - [c2]Ajith Amerasekera:
Concurrent Optimization of Technology and Design for Nano CMOS. VLSI Design 2007: 27 - 2002
- [c1]Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun:
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-153
1990 – 1999
- 1993
- [j1]Charvaka Duvvury, Ajith Amerasekera:
ESD: a pervasive reliability concern for IC technologies. Proc. IEEE 81(5): 690-702 (1993)
Coauthor Index
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