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ORCIDAngela Arapoyanni
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- affiliation: National and Kapodistrian University of Athens, Greece
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2010 – 2019
- 2016
[j16]Stefanos Valadimas, Yiorgos Tsiatouhas
, Angela Arapoyanni:
Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers 65(2): 654-663 (2016)- [c45]Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas:
Timing error mitigation in microprocessor cores. ICECS 2016: 772-775 - 2015
- [j15]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A current monitoring technique for IDDQ testing in digital integrated circuits. Integr. 50: 48-60 (2015) - [c44]John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li:
Fast deployment of alternate analog test using Bayesian model fusion. DATE 2015: 1030-1035 - [c43]John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE 2015: 1395-1400 - [c42]Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni:
On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS 2015: 1578-1581 - [c41]Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni:
Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics 2015: 419-423 - 2014
- [j14]Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos:
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63(5): 1277-1286 (2014) - [c40]Stefanos Valadimas, Angela Arapoyanni:
Timing Error Tolerance in Pipeline Based Core Designs. Panhellenic Conference on Informatics 2014: 31:1-31:6 - 2013
- [j13]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos:
Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. 29(6): 795-804 (2013) - [j12]John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas:
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1383-1394 (2013) - [j11]John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. 62(4): 732-742 (2013) - [c39]Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni:
NBTI aging tolerance in pipeline based designs NBTI. IOLTS 2013: 31-36 - 2012
- [c38]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans:
Single event upset tolerance in flip-flop based microprocessor cores. DFT 2012: 79-84 - [c37]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS 2012: 1-6 - [c36]Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS 2012: 961-964 - 2010
- [j10]Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1549-1558 (2010) - [c35]Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Build-In Self-Test technique for RF Mixers. DDECS 2010: 88-92 - [c34]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Timing error tolerance in nanometer ICs. IOLTS 2010: 283-288
2000 – 2009
- 2008
- [j9]Despina C. Moschou, M. A. Exarchos, Dimitrios N. Kouvatsos, George J. Papaioannou, Aggeliki Arapoyanni, Apostolos T. Voutsas:
Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique. Microelectron. Reliab. 48(8-9): 1544-1548 (2008) - [j8]Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57(8): 1032-1045 (2008) - 2007
- [c33]Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias:
A Scan Flip-Flop for Low-Power Scan Operation. ICECS 2007: 439-442 - [c32]Lampros Dermentzoglou, Anastasios Karagounis, Aggeliki Arapoyanni, Yiorgos Tsiatouhas:
An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers. ICECS 2007: 1119-1122 - [c31]Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni:
On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382 - 2006
- [j7]Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2647-2655 (2006) - [c30]Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS 2006: 692-695 - [c29]Y. Tsiatouhas, Angela Arapoyanni:
High fan-in differential current mirror logic. ISCAS 2006 - 2005
- [c28]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. ESSCIRC 2005: 471-474 - [c27]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
An embedded IDDQ testing circuit and technique. ICECS 2005: 1-4 - [c26]Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou:
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156 - [c25]Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni:
A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED 2005: 448-452 - 2004
- [j6]Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni:
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electron. Test. 20(2): 133-142 (2004) - [j5]Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20(5): 523-531 (2004) - [c24]Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI 2004: 293-296 - 2003
- [c23]Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis:
A low power NORA circuit design technique based on charge recycling. ICECS 2003: 224-227 - [c22]Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni:
A novel scheme for testing radio frequency voltage controlled oscillators. ICECS 2003: 595-598 - [c21]Christos Kokozidis, Stamatis Bouras, Angela Arapoyanni:
Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter. ICECS 2003: 794-797 - [c20]Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis:
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS 2003: 12-16 - [c19]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
An Embedded IDDQ Testing Architecture and Technique. ISQED 2003: 442-445 - 2002
- [j4]Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies. Integr. 31(2): 183-194 (2002) - [j3]Aristodemos Pnevmatikakis, Lampros Dermentzoglou, Aggeliki Arapoyanni:
Analog-to-Digital Interface for Heterodyne Receivers. J. Circuits Syst. Comput. 11(1): 57-72 (2002) - [j2]Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
Charge Pump Circuits for Low-voltage Applications. VLSI Design 15(1): 477-483 (2002) - [c18]Lampros Dermentzoglou, George Kamoulakos, Aggeliki Arapoyanni:
An extra low noise 1.8 GHz voltage controlled oscillator in 0.35 SiGe BiCMOS technology. ICECS 2002: 89-92 - [c17]Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis:
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW 2002: 56-60 - [c16]A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) 2002: 145-148 - [c15]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED 2002: 100-105 - 2001
- [c14]A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
New test pattern generation units for NPSF oriented memory built-in self test. ICECS 2001: 749-752 - [c13]A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni:
A new flash memory sense amplifier in 0.18 μm CMOS technology. ICECS 2001: 941-944 - [c12]Lampros Dermentzoglou, George Kamoulakos, Angela Arapoyanni:
A 0.35 μm SiGe BiCMOS front end for GSM low IF cellular receiver applications. ICECS 2001: 1607-1610 - [c11]Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
A CMOS differential logic for low-power and high-speed applications. ISCAS (4) 2001: 140-143 - [c10]Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni, Lampros Dermentzoglou:
A high-performance low-power static differential double edge-triggered flip-flop. ISCAS (4) 2001: 802-805 - 2000
- [j1]George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni:
Management of charge pump circuits. Integr. 30(1): 91-101 (2000) - [c9]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE 2000: 756 - [c8]Lampros Dermentzoglou, Aristodimos Pneumatikakis, Angela Arapoyanni, Yiannis Moisiadis:
A multimode extra high IF1 image rejection receiver for TDMA applications. ICECS 2000: 57-60 - [c7]A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni:
A test pattern generation unit for memory NPSF built-in self test. ICECS 2000: 425-428 - [c6]Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
High performance level restoration circuits for low-power reduced-swing interconnect schemes. ICECS 2000: 619-622 - [c5]Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
A state assignment algorithm for finite state machines. ICECS 2000: 823-826 - [c4]Yiannis Moisiadis, Ilias Bouras, Angela Arapoyanni:
A CMOS charge pump for low voltage operation. ISCAS 2000: 577-580 - [c3]Ilias Bouras, Yiannis Liaperdos, Angela Arapoyanni:
A high speed low power CMOS clock driver using charge recycling technique. ISCAS 2000: 657-660
1990 – 1999
- 1999
- [c2]Ioannis Moisiadis, Ilias Bouras, Constantin Papadas, Angela Arapoyanni:
Performance comparison of driver architectures in submicron CMOS and BiCMOS technologies for low voltage operation. ICECS 1999: 201-204 - [c1]Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
Novel domino logic designs. ICECS 1999: 213-216
Coauthor Index
aka: Lambros Dermentzoglou
aka: Th. Haniotakis
aka: Y. Tsiatouhas
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