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ORCID2. TPCD 1994: Bad Herrenalb, Germany
- Ramayya Kumar, Thomas Kropf:
Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings. Lecture Notes in Computer Science 901, Springer 1994, ISBN 3-540-59047-1 - Thomas Kropf:
Benchmark-Circuits for Hardware-Verification. 1-12
Research Papers
- Mark D. Aagaard, Miriam Leeser
:
Reasoning About Pipelines with Structural Hazards. 13-32 - Phillip J. Windley, Michael L. Coe:
A Correctness Model for Pipelined Multiprocessors. 33-51 - John W. O'Leary, Miriam Leeser, Jason Hickey, Mark D. Aagaard:
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. 52-71 - Laurence Pierre:
An Automatic Generalization Method for the Inductive Proof of Replicated and Parallel Architectures. 72-91 - Zheng Zhu:
A Compositional Circuit Model and Verification by Composition. 92-109 - C. A. J. van Eijk, Geert Janssen:
Exploiting Structural Similarities in a BDD-Based Verification Method. 110-125 - Steven D. Johnson, Paul S. Miner, Albert John Camilleri:
Studies of the Single Pulser in Various Reasoning Systems. 126-145 - Michael Kishinevsky, Jørgen Staunstrup:
Mechanized Verification of Speed-independence. 146-164 - Junji Kitamichi, Sumio Morioka, Teruo Higashino, Kenichi Taniguchi:
Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. 165-184 - Niels Maretti:
Mechanized Verification of Refinement. 185-202 - David Cyrluk, S. Rajan, Natarajan Shankar, Mandayam K. Srivas:
Effective Theorem Proving for Hardware Verification. 203-222 - Thomas Kropf, Klaus Schneider, Ramayya Kumar:
A Formal Framework for High Level Synthesis. 223-238
Tutorial Papers
- Niels Mellergaard, Jørgen Staunstrup:
Tutorial on Design Verification with Synchronized Transitions. 239-257 - Sam Owre, John M. Rushby, Natarajan Shankar, Mandayam K. Srivas:
A Tutorial on Using PVS for Hardware Verification. 258-279
Short Papers
- Holger Busch:
A Reduced Instruction Set Proof Environment. 280-285 - G. Bezzi, Massimo Bombana, Patrizia Cavalloro, Salvatore Conigliaro, Giuseppe Zaza:
Quantitative Evaluation of Formal Based Synthesis in ASIC Design. 286-291 - Michel Allemand:
Formal Verification of Characteristic Properties. 292-297 - Kathi Fisler:
Extending Formal Reasoning with Support for Hardware Diagrams. 298-303
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