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2020 – today
- 2024
[j12]Francesco Vigli, Marcello Barbirotta
, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri:
A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection. IEEE Access 12: 30495-30506 (2024)- [j11]Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri:
Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems. IEEE Access 12: 95720-95735 (2024) - [j10]Gennaro Bellizzi, Alessio Buzzin, Lorenzo Crocco, Antonio Mastrandrea, Noemi Zeni, Sabrina Zumbo, Marta Cavagnaro:
A Simple Microwave Imaging System for Food Product Inspection through a Symmetry-Based Microwave Imaging Approach. Sensors 24(1): 99 (2024) - [j9]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri:
Design, Implementation and Evaluation of a New Variable Latency Integer Division Scheme. IEEE Trans. Computers 73(7): 1767-1779 (2024) - [c30]Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri:
Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor. DFT 2024: 1-6 - [c29]Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Francesco Menichelli, Abdallah Cheikh, Mauro Olivieri:
Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation. DFT 2024: 1-6 - [c28]Marco Angioli, Saeid Jamili, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Antonello Rosato, Mauro Olivieri:
AeneasHDC: An Automatic Framework for Deploying Hyperdimensional Computing Models on FPGAs. IJCNN 2024: 1-8 - [c27]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Mauro Olivieri:
Exploring Variable Latency Dividers in Vector Hardware Accelerators. PRIME 2024: 1-4 - 2023
- [c26]Marcello Barbirotta, Francesco Menichelli, Antonio Mastrandrea, Abdallah Cheikh, Marco Angioli, Saeid Jamili, Mauro Olivieri:
Heterogeneous Tightly-Coupled Dual Core Architecture Against Single Event Effects. ApplePies 2023: 15-21 - [c25]Saeid Jamili, Antonio Mastrandrea, Abdallah Cheikh, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri:
A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach. ApplePies 2023: 36-41 - [c24]Marcello Barbirotta, Marco Angioli, Antonio Mastrandrea, Abdallah Cheikh, Saeid Jamili, Francesco Menichelli, Mauro Olivieri:
Single Event Transient Reliability Analysis on a Fault-Tolerant RISC-V Microprocessor Design. ApplePies 2023: 42-48 - [c23]Marco Angioli, Marcello Barbirotta, Antonio Mastrandrea, Saeid Jamili, Mauro Olivieri:
Automatic Hardware Accelerators Reconfiguration through LinearUCB Algorithms on a RISC-V Processor. PRIME 2023: 169-172 - 2022
- [j8]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors. IEEE Access 10: 126074-126088 (2022) - [c22]Silvia Casalinuovo, Alessio Buzzin, Antonio Mastrandrea, Ivan Mazzetta, Marcello Barbirotta, Lorenzo Iannascoli, Augusto Nascetti, Giampiero de Cesare, Donatella Puglisi, Domenico Caputo:
3D-Printed Face Mask with Integrated Sensors as Protective and Monitoring Tool. AISEM 2022: 40-45 - [c21]Marco Angioli, Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Saeid Jamili, Mauro Olivieri:
Contextual Bandits Algorithms for Reconfigurable Hardware Accelerators. ApplePies 2022: 149-154 - [c20]Saeid Jamili, Abdallah Cheikh, Antonio Mastrandrea, Marcello Barbirotta, Francesco Menichelli, Marco Angioli, Mauro Olivieri:
Implementation of Dynamic Acceleration Unit Exchange on a RISC-V Soft-Processor. ApplePies 2022: 300-306 - [c19]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Analysis of a Fault Tolerant Edge-Computing Microarchitecture Exploiting Vector Acceleration. PRIME 2022: 237-240 - 2021
- [j7]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri:
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores. IEEE Micro 41(2): 64-71 (2021) - [j6]Nicola Bombieri, Silvia Scaffeo, Antonio Mastrandrea, Simone Caligola, Tommaso Carlucci, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno:
SystemC Implementation of Stochastic Petri Nets for Simulation and Parameterization of Biological Networks. ACM Trans. Embed. Comput. Syst. 20(4): 31:1-31:20 (2021) - [c18]Alessandro Zompanti, Anna Sabatini, Simone Grasso, Giorgio Pennazza, Antonio Mastrandrea, Giuseppe Ferri, Gianluca Barile, Marco Santonico:
A Ladder Network Theoretical Approach for the Automatic Monitoring of Distributed Sensors. AISEM 2021: 333-339 - [c17]Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri:
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design. DFT 2021: 1-4 - 2020
- [c16]Marcello Barbirotta, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Luigi Blasi, Abdallah Cheikh, Stefano Sordillo, Fabio Di Gennaro, Mauro Olivieri:
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment. DFT 2020: 1-6 - [i3]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Giuseppe Scotti, Mauro Olivieri:
Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores. CoRR abs/2007.09109 (2020)
2010 – 2019
- 2019
- [j5]Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Full System Emulation of Approximate Memory Platforms with AppropinQuo. J. Low Power Electron. 15(1): 30-39 (2019) - [c15]Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Quality Aware Selective ECC for Approximate DRAM. ApplePies 2019: 109-116 - [c14]Luigi Blasi, Francesco Vigli, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
A RISC-V Fault-Tolerant Microcontroller Core Architecture Based on a Hardware Thread Full/Partial Protection and a Thread-Controlled Watch-Dog Timer. ApplePies 2019: 505-511 - [c13]Abdallah Cheikh, Stefano Sordillo, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
Efficient Mathematical Accelerator Design Coupled with an Interleaved Multi-threading RISC-V Microprocessor. ApplePies 2019: 529-539 - [c12]Nicola Bombieri, Antonio Mastrandrea, Silvia Scaffeo, Simone Caligola, Franco Fummi, Carlo Laudanna, Gabriela Constantin, Rosalba Giugno:
On the Simulation and Automatic Parametrization of Metabolic Networks Through Electronic Design Automation. CIBB 2019: 323-334 - [c11]Andrea Bartolini, Davide Rossi, Antonio Mastrandrea, Christian Conficoni, Simone Benatti, Andrea Tilli, Luca Benini:
A PULP-based Parallel Power Controller for Future Exascale Systems. ICECS 2019: 771-774 - [c10]Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Quality Aware Approximate Memory in RISC-V Linux Kernel. PRIME 2019: 177-180 - 2018
- [c9]Giulia Stazi, Federica Silvestri, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Synthesis Time Reconfigurable Floating Point Unit for Transprecision Computing. ApplePies 2018: 261-267 - [c8]Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Approximate Memory Support for Linux Early Allocators in ARM Architectures. ApplePies 2018: 429-435 - [c7]Mauro Olivieri, Usman Khalid, Antonio Mastrandrea, Francesco Menichelli:
Characterizing noise pulse effects on the power consumption of idle digital cells. ISCAS 2018: 1-5 - [c6]Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
AppropinQuo: A Platform Emulator for Exploring the Approximate Memory Design Space. NGCAS 2018: 66-69 - [c5]Giulia Stazi, Lorenzo Adani, Antonio Mastrandrea, Mauro Olivieri, Francesco Menichelli:
Impact of Approximate Memory Data Allocation on a H.264 Software Video Encoder. ISC Workshops 2018: 545-553 - 2017
- [c4]Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
The Microarchitecture of a Multi-threaded RISC-V Compliant Processing Core Family for IoT End-Nodes. ApplePies 2017: 89-97 - [c3]Mauro Olivieri, Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli:
Investigation on the Optimal Pipeline Organization in RISC-V Multi-threaded Soft Processor Cores. NGCAS 2017: 45-48 - [i2]Abdallah Cheikh, Gianmarco Cerutti, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri:
The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes. CoRR abs/1712.04902 (2017) - [i1]Usman Khalid, Antonio Mastrandrea, Mauro Olivieri:
Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops. CoRR abs/1712.06934 (2017) - 2016
- [c2]Francesco Menichelli, Giulia Stazi, Antonio Mastrandrea, Mauro Olivieri:
An Emulator for Approximate Memory Platforms Based on QEmu. ApplePies 2016: 153-159 - 2015
- [j4]Usman Khalid, Antonio Mastrandrea, Mauro Olivieri:
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops. Microelectron. Reliab. 55(12): 2614-2626 (2015) - 2014
- [j3]Mauro Olivieri, Antonio Mastrandrea:
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1429-1440 (2014) - [j2]Zia Abbas, Antonio Mastrandrea, Mauro Olivieri:
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2549-2560 (2014) - [c1]Usman Khalid, Antonio Mastrandrea, Mauro Olivieri:
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops. DSD 2014: 488-495 - 2013
- [j1]Mauro Olivieri, Antonio Mastrandrea:
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. VLSI Design 2013: 785281:1-785281:12 (2013)
Coauthor Index
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