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ORCIDDustin Richmond
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2020 – today
- 2024
[j5]Colin Drewes
, Tyler Sheaves, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond:
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters. ACM Trans. Reconfigurable Technol. Syst. 17(3): 49:1-49:30 (2024)- [c18]Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond:
Pentimento: Data Remanence in Cloud FPGAs. ASPLOS (2) 2024: 862-878 - [c17]Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor:
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA 2024: 770-784 - [i3]Rui-Jie Zhu, Yu Zhang, Ethan Sifferman, Tyler Sheaves, Yiqiao Wang, Dustin Richmond, Peng Zhou, Jason K. Eshraghian:
Scalable MatMul-free Language Modeling. CoRR abs/2406.02528 (2024) - 2023
- [c16]Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Mark Oskin, Christopher Batten:
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. ASPLOS (3) 2023: 46-58 - [c15]Colin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond:
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. FPGA 2023: 111-122 - [i2]Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond:
Pentimento: Data Remanence in Cloud FPGAs. CoRR abs/2303.17881 (2023) - 2022
- [j4]Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten:
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1620-1635 (2022) - 2021
- [c14]Mustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond:
Classifying Computations on Multi-Tenant FPGAs. DAC 2021: 1261-1266 - [c13]Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond:
A Tunable Dual-Edge Time-to-Digital Converter. FCCM 2021: 253 - [c12]Mustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond, Ryan Kastner:
Classifying Computations on Multi-Tenant FPGAs. FPGA 2021: 227 - [c11]Ajay Brahmakshatriya, Emily Furst, Victor A. Ying, Claire Hsu, Changwan Hong, Max Ruttenberg, Yunming Zhang, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Julian Shun, Mark Oskin, Daniel Sánchez, Saman P. Amarasinghe:
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. ISCA 2021: 429-442 - 2020
- [j3]Michael Bedford Taylor, Luis Vega, Moein Khazraee, Ikuo Magaki, Scott Davidson, Dustin Richmond:
ASIC clouds: specializing the datacenter for planet-scale applications. Commun. ACM 63(7): 103-109 (2020) - [c10]Dai Cheol Jung, Scott Davidson, Chun Zhao, Dustin Richmond, Michael Bedford Taylor:
Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper. NOCS 2020: 1-8 - [c9]Daniel Petrisko, Chun Zhao, Scott Davidson, Paul Gao, Dustin Richmond, Michael Bedford Taylor:
NoC Symbiosis : (Special Session Paper). NOCS 2020: 1-8
2010 – 2019
- 2019
- [c8]Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski:
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - 2018
- [b1]Dustin Alexander Richmond:
Hardware Development for Non-Hardware Engineers. University of California, San Diego, USA, 2018 - [j2]Dustin Richmond, Alric Althoff, Ryan Kastner:
Synthesizable Higher-Order Functions for C++. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2835-2844 (2018) - [c7]Brennan Cain, Zain Merchant, Indira Avendano, Dustin Richmond, Ryan Kastner:
PynqCopter - An Open-source FPGA Overlay for UAVs. IEEE BigData 2018: 2491-2498 - [c6]Dustin Richmond, Michael Barrow, Ryan Kastner:
Everyone's a Critic: A Tool for Exploring RISC-V Projects. FPL 2018: 260-264 - 2017
- [c5]Dajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner:
A streaming clustering approach using a heterogeneous system for big data analysis. ICCAD 2017: 699-706 - 2016
- [c4]Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner:
Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. FCCM 2016: 21-24 - [c3]Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner:
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. FPGA 2016: 195-204 - 2015
- [j1]Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner:
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. ACM Trans. Reconfigurable Technol. Syst. 8(4): 22:1-22:23 (2015) - 2014
- [c2]Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner:
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. FPT 2014: 326-329 - [i1]Janarbek Matai, Dustin Richmond, Dajung Lee, Ryan Kastner:
Enabling FPGAs for the Masses. CoRR abs/1408.5870 (2014) - 2013
- [c1]Dustin Richmond, Ryan Kastner, Ali Irturk, John McGarry:
A FPGA design for high speed feature extraction from a compressed measurement stream. FPL 2013: 1-8
Coauthor Index
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last updated on 2024-11-18 20:47 CET by the dblp team
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