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ORCIDJin-Fu Li 0001
Person information
- affiliation: National Central University, Department of Electrical Engineering, Taoyuan, Taiwan
- affiliation (PhD 2002): National Tsing Hua University, Hsinchu, Taiwan
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2020 – today
- 2024
[c91]Jin-Fu Li:
Special Session: Testing of Digital Computing-In Memories with MAC Function. DFT 2024: 1-5- [c90]Pei-Yun Lin, Jin-Fu Li:
Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs. ETS 2024: 1-4 - [c89]Yi-Chun Huang, Pei-Yun Lin, Jin-Fu Li, Hong-Siang Fu, Yung-Ping Lee:
Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips. ITC 2024: 149-156 - 2023
- [c88]Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. ASP-DAC 2023: 13-18 - [c87]Shih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li:
Hardware Trojans of Computing-In-Memories: Issues and Methods. DFT 2023: 1-6 - [c86]Jin-Fu Li:
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability. DFT 2023: 1-6 - [c85]Meng-Shan Wu, Yen-Lin Chua, Jin-Fu Li, Yun-Ting Chuan, Shih-Hsu Huang:
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. ITC-Asia 2023: 1-6 - 2022
- [c84]Jin-Fu Li, Jing-Jia Liou:
Foreword: ATS 2022. ATS 2022: x - [c83]Jin-Fu Li:
Design and Test of Computing-In Memories. ISOCC 2022: 157-158 - [c82]Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li:
Design and Dataflow for Multibit SRAM-Based MAC Operations. ISOCC 2022: 159-160 - [c81]Ze-Wei Pan, Jin-Fu Li:
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs. ITC 2022: 489-493 - [c80]Yu-Cheng Yang, Jin-Fu Li:
Fault Modeling and Testing of RRAM-based Computing-In Memories. ITC-Asia 2022: 7-12 - [c79]Jin-Fu Li:
Testing and Reliability of Computing-In Memories: Solutions and Challenges. ITC-Asia 2022: 55-60 - 2021
- [c78]Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. DFT 2021: 1-4 - [c77]Yung-Yu Tsai, Jin-Fu Li:
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults. SoCC 2021: 272-277 - 2020
- [c76]Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun:
Testing of Configurable 8T SRAMs for In-Memory Computing. ATS 2020: 1-5 - [c75]Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46
2010 – 2019
- 2019
- [c74]Fan-Hsuan Tang, Hsu-Yu Kao, Shih-Hsu Huang, Jin-Fu Li:
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered. 3DIC 2019: 1-4 - [c73]Wei-Hsuan Yang, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun, Shih-Hsu Huang:
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. 3DIC 2019: 1-3 - [c72]Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Testing stuck-open faults of priority address encoder in content addressable memories. ASP-DAC 2019: 347-351 - [c71]Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Testing of In-Memory-Computing 8T SRAMs. DFT 2019: 1-4 - 2018
- [j39]Jin-Fu Li
, Jiun-Lang Huang:
Conference Reports: Report on 2017 IEEE Asian Test Symposium. IEEE Des. Test 35(2): 103-104 (2018) - [c70]Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250 - [c69]Li-Wei Deng, Jin-Fu Li, Yong-Xiao Chen:
Modeling and testing comparison faults of memristive ternary content addressable memories. ETS 2018: 1-6 - [c68]Yu-Ting Li, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Diagnosis of Resistive Nonvolatile-8T SRAMs. ISOCC 2018: 23-24 - 2017
- [c67]Chia-Ming Chang, Yong-Xiao Chen, Jin-Fu Li:
A built-in self-test scheme for classifying refresh periods of DRAMs. ETS 2017: 1-2 - [c66]Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111 - 2016
- [c65]Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS 2016: 281-286 - [c64]Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li:
A built-in method for measuring the delay of TSVs in 3D ICs. ETS 2016: 1-6 - [c63]Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC 2016: 1-7 - [c62]Yu-Ting Li, Yong-Xiao Chen, Jin-Fu Li:
Fault modeling and testing of resistive nonvolatile-8T SRAMs. VTS 2016: 1-6 - 2015
- [j38]Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test 32(4): 59-70 (2015) - [j37]Chih-Sheng Hou, Jin-Fu Li:
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1720-1728 (2015) - [c61]Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li:
Testing Inter-Word Coupling Faults of Wide I/O DRAMs. ATS 2015: 67-72 - [c60]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - [c59]Yong-Xiao Chen, Jin-Fu Li:
Fault modeling and testing of 1T1R memristor memories. VTS 2015: 1-6 - 2014
- [j36]Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. J. Electron. Test. 30(6): 643-652 (2014) - [j35]Chih-Sheng Hou, Jin-Fu Li, Ting-Jun Fu:
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2020-2024 (2014) - [j34]Yu-Jen Huang, Jin-Fu Li:
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs. ACM Trans. Embed. Comput. Syst. 13(3s): 106:1-106:22 (2014) - [c58]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c57]Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo:
Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS 2014: 143-148 - [c56]Yong-Xiao Chen, Jin-Fu Li:
Testing of Non-volatile Logic-Based System Chips. ATS 2014: 224-229 - [c55]Iris Hui-Ru Jiang, Natarajan Viswanathan, Tai-Chen Chen, Jin-Fu Li:
The overview of 2014 CAD contest at ICCAD. ICCAD 2014: 356 - 2013
- [j33]Chun-Kai Lai, Yu-Jen Huang, Jin-Fu Li:
A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function. J. Inf. Sci. Eng. 29(3): 493-507 (2013) - [j32]Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li:
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 572-583 (2013) - [c54]Chi-Chun Yang, Che-Wei Chou, Jin-Fu Li:
A TSV Repair Scheme Using Enhanced Test Access Architecture for 3-D ICs. Asian Test Symposium 2013: 7-12 - [c53]Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. Asian Test Symposium 2013: 221-226 - [c52]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c51]Chih-Sheng Hou, Jin-Fu Li:
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs. VTS 2013: 1-6 - [c50]Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. VTS 2013: 1 - [c49]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [j31]Jin-Fu Li:
Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells. IEEE Trans. Computers 61(11): 1576-1587 (2012) - [j30]Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng:
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 930-940 (2012) - [j29]Yu-Jen Huang, Jin-Fu Li:
Built-In Self-Repair Scheme for the TSVs in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1600-1613 (2012) - [j28]Shun-Hsun Yang, Yu-Jen Huang, Jin-Fu Li:
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1909-1913 (2012) - [j27]Yu-Jen Huang, Jin-Fu Li:
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2123-2127 (2012) - [c48]Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li:
On test and repair of 3D random access memory. ASP-DAC 2012: 744-749 - [c47]Chih-Sheng Hou, Jin-Fu Li:
Disturbance fault testing on various NAND flash memories. ETS 2012: 1 - [c46]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - [c45]Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li:
Area and reliability efficient ECC scheme for 3D RAMs. VLSI-DAT 2012: 1-4 - [c44]Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou:
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. VLSI-DAT 2012: 1-4 - [c43]Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li:
Test cost optimization technique for the pre-bond test of 3D ICs. VTS 2012: 102-107 - 2011
- [j26]Tsu-Wei Tseng, Jin-Fu Li:
SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. J. Inf. Sci. Eng. 27(2): 643-656 (2011) - [j25]Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng:
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1731-1743 (2011) - [j24]Tsu-Wei Tseng, Jin-Fu Li:
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1983-1995 (2011) - [c42]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - 2010
- [j23]Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou:
A Built-in Method to Repair SoC RAMs in Parallel. IEEE Des. Test Comput. 27(6): 46-57 (2010) - [j22]Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li:
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1628-1639 (2010) - [j21]Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu:
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1843-1847 (2010) - [j20]Jin-Fu Li:
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 912-920 (2010) - [j19]Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu:
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 921-932 (2010) - [j18]Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou:
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1361-1366 (2010) - [c41]Jin-Fu Li, Cheng-Wen Wu:
Is 3D integration an opportunity or just a hype? ASP-DAC 2010: 541-543 - [c40]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c39]Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou:
Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. DELTA 2010: 3-7 - [c38]Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li:
A low-cost and scalable test architecture for multi-core chips. ETS 2010: 30-35 - [c37]Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li:
A low-cost built-in self-test scheme for an array of memories. ETS 2010: 75-80 - [c36]Yu-Jen Huang, Yun-Chao You, Jin-Fu Li:
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. SoCC 2010: 236-240 - [c35]Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li:
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. VTS 2010: 21-26
2000 – 2009
- 2009
- [j17]Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li:
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks. IEEE Micro 29(5): 46-55 (2009) - [c34]Yu-Jen Huang, Jin-Fu Li:
Testability Exploration of 3-D RAMs and CAMs. Asian Test Symposium 2009: 397-402 - [c33]Hsing-Chen Lu, Jin-Fu Li:
A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC. ISCAS 2009: 1997-2000 - [c32]Bing-Wei Huang, Jin-Fu Li:
Efficient diagnosis algorithms for drowsy SRAMs. ISQED 2009: 276-279 - [c31]Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li:
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. VTS 2009: 15-20 - 2008
- [j16]Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang:
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J. Electron. Test. 24(1-3): 181-192 (2008) - [j15]Hong-Ming Shieh, Jin-Fu Li:
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs. IEICE Trans. Inf. Syst. 91-D(10): 2428-2434 (2008) - [c30]Yu-Jen Huang, Jin-Fu Li:
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips. ATS 2008: 357-362 - [c29]Tsu-Wei Tseng, Jin-Fu Li:
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. ITC 2008: 1-9 - 2007
- [j14]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu:
Raisin: Redundancy Analysis Algorithm Simulation. IEEE Des. Test Comput. 24(4): 386-396 (2007) - [j13]Jin-Fu Li, Chao-Da Huang:
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2703-2711 (2007) - [j12]Yu-Jen Huang, Jin-Fu Li:
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. IET Comput. Digit. Tech. 1(3): 246-255 (2007) - [j11]Jin-Fu Li:
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 919-931 (2007) - [j10]Jin-Fu Li:
Transparent-Test Methodologies for Random Access Memories Without/With ECC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1888-1893 (2007) - [j9]Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng:
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1135-1143 (2007) - [c28]Hsiang-Huang Wu, Jin-Fu Li, Chi-Feng Wu, Cheng-Wen Wu:
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs. ATS 2007: 355-360 - [c27]Jin-Fu Li:
Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells. ATS 2007: 501-506 - [c26]Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey:
Design of cost-efficient memory-based FFT processors using single-port memories. SoCC 2007: 29-32 - [c25]Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng:
Diagnosing scan chains using SAT-based diagnostic pattern generation. SoCC 2007: 273-276 - [c24]Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen:
A Built-In Self-Repair Scheme for Multiport RAMs. VTS 2007: 355-360 - [i1]Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. CoRR abs/0710.4747 (2007) - 2006
- [c23]Jin-Fu Li, Chun-Hsien Wu:
Verification Methodology for Self-Repairable Memory Systems. ATS 2006: 109-114 - [c22]Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang:
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. DATE 2006: 53-58 - [c21]Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li:
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. DFT 2006: 362-370 - [c20]Yu-Jen Huang, Jin-Fu Li:
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. ETS 2006: 55-62 - [c19]Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen:
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. ITC 2006: 1-9 - 2005
- [j8]Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu:
A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 742-745 (2005) - [c18]Jin-Fu Li:
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. ASP-DAC 2005: 65-70 - [c17]Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. DATE 2005: 574-579 - [c16]Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang:
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. ISCAS (1) 2005: 77-80 - [c15]Jin-Fu Li:
Testing priority address encoder faults of content addressable memories. ITC 2005: 8 - [c14]Jin-Fu Li, Yu-Jane Huang:
An error detection and correction scheme for RAMs with partial-write function. MTDT 2005: 115-120 - [c13]Jin-Fu Li, Chou-Kun Lin:
Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. VTS 2005: 60-65 - 2004
- [j7]Jin-Fu Li:
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults. IEICE Trans. Inf. Syst. 87-D(3): 601-608 (2004) - [c12]Jin-Fu Li, Chao-Da Huang:
An Efficient Diagnosis Scheme for Random Access Memories. Asian Test Symposium 2004: 277-282 - [c11]Jin-Fu Li, Chih-Chiang Hsu:
Efficient Test Methodologies for Conditional Sum Adders. Asian Test Symposium 2004: 319-324 - 2003
- [j6]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. J. Electron. Test. 19(2): 207-215 (2003) - [j5]Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu:
Built-in redundancy analysis for memory yield improvement. IEEE Trans. Reliab. 52(4): 386-399 (2003) - [c10]Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC 2003: 393-402 - [c9]Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li:
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT 2003: 53- - 2002
- [j4]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. J. Electron. Test. 18(4-5): 515-527 (2002) - [j3]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electron. Test. 18(6): 637-647 (2002) - [j2]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5): 69-81 (2002) - [j1]Jin-Fu Li, Cheng-Wen Wu:
Efficient FFT network testing and diagnosis schemes. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 267-278 (2002) - [c8]Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs. DATE 2002: 486-490 - [c7]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu:
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW 2002: 262- - [c6]Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu:
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT 2002: 68- - [c5]Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu:
Testing and Diagnosing Embedded Content Addressable Memories. VTS 2002: 389-394 - 2001
- [c4]Jin-Fu Li, Cheng-Wen Wu:
Memory fault diagnosis by syndrome compression. DATE 2001: 97-101 - [c3]Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767 - 2000
- [c2]Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50
1990 – 1999
- 1999
- [c1]Jin-Fu Li, Cheng-Wen Wu:
Testable and Fault Tolerant Design for FFT Networks. DFT 1999: 201-209
Coauthor Index
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Citation data
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load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
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last updated on 2025-01-20 22:58 CET by the dblp team
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