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ORCIDPavan Kumar Hanumolu
Person information
- affiliation: University of Illinois, Urbana-Champaign, IL, USA
- affiliation (PhD 2006): Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA
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Journal Articles
- 2023
[j85]Yongxin Li
, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Kyu-Sang Park, Ruhao Xia, Pavan Kumar Hanumolu:
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. IEEE J. Solid State Circuits 58(3): 785-795 (2023)- [j84]Kyu-Sang Park, Amr Khashaba, Ahmed E. AbdelRahman, Yongxin Li, Tianyu Wang, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu:
A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C. IEEE J. Solid State Circuits 58(7): 2064-2074 (2023) - [j83]Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang, Ahmed E. AbdelRahman, Pavan Kumar Hanumolu:
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C. IEEE J. Solid State Circuits 58(12): 3459-3469 (2023) - 2022
- [j82]Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu:
A 3.2-GHz 405 fsrms Jitter -237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer. IEEE J. Solid State Circuits 57(3): 698-708 (2022) - [j81]Amr Khashaba, Junheng Zhu, Nilanjan Pal, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A 32-MHz, 34-μW Temperature-Compensated RC Oscillator Using Pulse Density Modulated Resistors. IEEE J. Solid State Circuits 57(5): 1470-1479 (2022) - [j80]Pavan Kumar Hanumolu:
Guest Editorial Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 57(8): 2279 (2022) - [j79]Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu:
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. IEEE J. Solid State Circuits 57(8): 2521-2531 (2022) - 2021
- [j78]Pavan Kumar Hanumolu:
New Associate Editors. IEEE J. Solid State Circuits 56(9): 2607-2608 (2021) - [j77]Mostafa Gamal Ahmed, Dongwook Kim, Romesh Kumar Nandwana, Ahmed Elkholy, Kadaba R. Lakshmikumar, Pavan Kumar Hanumolu:
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. IEEE J. Solid State Circuits 56(9): 2795-2803 (2021) - [j76]Pavan Kumar Hanumolu:
New Associate Editor. IEEE J. Solid State Circuits 56(10): 2899 (2021) - [j75]Nilanjan Pal, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications. IEEE J. Solid State Circuits 56(11): 3499-3510 (2021) - 2020
- [j74]Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques. IEEE J. Solid State Circuits 55(3): 592-601 (2020) - [j73]Pavan Kumar Hanumolu:
New Associate Editors. IEEE J. Solid State Circuits 55(6): 1439-1440 (2020) - [j72]Dongwook Kim, Mostafa Gamal Ahmed, Woo-Seok Choi, Ahmed Elkholy, Pavan Kumar Hanumolu:
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 55(8): 2196-2205 (2020) - [j71]Pourya Assem, Wen-Chuen Liu, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski:
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS. IEEE J. Solid State Circuits 55(9): 2513-2528 (2020) - 2019
- [j70]Karim M. Megawer, Ahmed Elkholy, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu:
Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers. IEEE J. Solid State Circuits 54(1): 65-74 (2019) - [j69]Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu:
A 15-Gb/s Sub-Baud-Rate Digital CDR. IEEE J. Solid State Circuits 54(3): 685-695 (2019) - [j68]Mostafa Gamal Ahmed, Tam N. Huynh, Christopher Williams, Yong Wang, Pavan Kumar Hanumolu, Alexander V. Rylyakov:
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers. IEEE J. Solid State Circuits 54(3): 834-844 (2019) - [j67]Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. IEEE J. Solid State Circuits 54(7): 2049-2058 (2019) - [j66]Pavan Kumar Hanumolu:
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 54(8): 2108 (2019) - [j65]Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. IEEE J. Solid State Circuits 54(8): 2186-2194 (2019) - [j64]Karim M. Megawer, Nilanjan Pal, Ahmed Elkholy, Mostafa Gamal Ahmed, Amr Khashaba, Danielle Griffith, Pavan Kumar Hanumolu:
A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection. IEEE J. Solid State Circuits 54(12): 3257-3268 (2019) - [j63]Noyan Cem Sevüktekin, Lav R. Varshney, Pavan Kumar Hanumolu, Andrew C. Singer:
Signal Processing Foundations for Time-Based Signal Representations: Neurobiological parallels to engineered systems designed for energy efficiency or hardware simplicity. IEEE Signal Process. Mag. 36(6): 38-50 (2019) - [j62]Tianyu Wang, Danielle Griffith, Mostafa Gamal Ahmed, Junheng Zhu, Da Wei, Ahmed Elkholy, Ahmed Elmallah, Pavan Kumar Hanumolu:
A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation. IEEE Trans. Circuits Syst. II Express Briefs 66-II(8): 1297-1301 (2019) - 2018
- [j61]Mostafa Gamal Ahmed, Mrunmay Talegaonkar, Ahmed Elkholy, Guanghua Shu, Ahmed Elmallah, Alexander V. Rylyakov, Pavan Kumar Hanumolu:
A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS. IEEE J. Solid State Circuits 53(2): 445-457 (2018) - [j60]Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes. IEEE J. Solid State Circuits 53(3): 814-824 (2018) - [j59]Da Wei, Tejasvi Anand, Guanghua Shu, José E. Schutt-Ainé, Pavan Kumar Hanumolu:
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects. IEEE J. Solid State Circuits 53(3): 873-883 (2018) - [j58]Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu:
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation. IEEE J. Solid State Circuits 53(3): 884-895 (2018) - [j57]Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE J. Solid State Circuits 53(6): 1806-1817 (2018) - [j56]Ahmed Elkholy, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier. IEEE J. Solid State Circuits 53(6): 1818-1829 (2018) - [j55]Or Ordentlich, Gizem Tabak, Pavan Kumar Hanumolu, Andrew C. Singer, Gregory W. Wornell:
A Modulo-Based Architecture for Analog-to-Digital Conversion. IEEE J. Sel. Top. Signal Process. 12(5): 825-840 (2018) - 2017
- [j54]Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu:
A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS. IEEE J. Solid State Circuits 52(1): 8-20 (2017) - [j53]Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52(5): 1399-1411 (2017) - [j52]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52(9): 2306-2320 (2017) - [j51]Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu:
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 283-295 (2017) - 2016
- [j50]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu:
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51(2): 428-439 (2016) - [j49]Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu:
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits 51(8): 1771-1784 (2016) - [j48]Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu:
A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity. IEEE J. Solid State Circuits 51(11): 2651-2663 (2016) - 2015
- [j47]Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50(3): 737-748 (2015) - [j46]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50(4): 867-881 (2015) - [j45]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50(4): 882-895 (2015) - [j44]Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
High Frequency Buck Converter Design Using Time-Based Control Techniques. IEEE J. Solid State Circuits 50(4): 990-1001 (2015) - [j43]Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications. IEEE J. Solid State Circuits 50(8): 1785-1795 (2015) - [j42]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits 50(12): 2814-2824 (2015) - [j41]Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits 50(12): 3101-3119 (2015) - [j40]Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers. IEEE J. Solid State Circuits 50(12): 3160-3174 (2015) - 2014
- [j39]Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu:
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs. IEEE J. Solid State Circuits 49(4): 950-960 (2014) - [j38]Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49(4): 1036-1047 (2014) - [j37]Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. IEEE J. Solid State Circuits 49(5): 1184-1197 (2014) - [j36]Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu:
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits 49(8): 1827-1836 (2014) - [j35]Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu:
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits 49(10): 2228-2242 (2014) - [j34]Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits 49(10): 2243-2258 (2014) - [j33]Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu:
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 49(12): 2743-2747 (2014) - 2013
- [j32]Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez:
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits 48(2): 487-501 (2013) - [j31]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits 48(6): 1416-1428 (2013) - 2012
- [j30]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47(12): 2916-2927 (2012) - [j29]Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
Analog Filter Design Using Ring Oscillator Integrators. IEEE J. Solid State Circuits 47(12): 3120-3129 (2012) - [j28]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1604-1613 (2012) - [j27]Naga Sasidhar, David Gubbins, Pavan Kumar Hanumolu, Un-Ku Moon:
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 558-562 (2012) - 2011
- [j26]Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits 46(8): 1870-1880 (2011) - [j25]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits 46(12): 2759-2771 (2011) - [j24]Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu:
A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique. IEEE J. Solid State Circuits 46(12): 2772-2783 (2011) - [j23]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits 46(12): 3150-3162 (2011) - [j22]Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits 46(12): 3163-3173 (2011) - [j21]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(5): 1089-1098 (2011) - [j20]Yan Wang, Pavan Kumar Hanumolu, Gabor C. Temes:
Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7): 1518-1530 (2011) - 2010
- [j19]David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
Continuous-Time Input Pipeline ADCs. IEEE J. Solid State Circuits 45(8): 1456-1468 (2010) - [j18]Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(11): 2880-2889 (2010) - 2009
- [j17]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits 44(2): 427-435 (2009) - [j16]Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture. IEEE J. Solid State Circuits 44(8): 2169-2181 (2009) - [j15]Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 10 MS/s 11-bit 0.19 mm2 Algorithmic ADC With Improved Clocking Scheme. IEEE J. Solid State Circuits 44(9): 2348-2355 (2009) - [j14]Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon:
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback. IEEE J. Solid State Circuits 44(9): 2392-2401 (2009) - [j13]Ankur Agrawal, Andrew Liu, Pavan Kumar Hanumolu, Gu-Yeon Wei:
An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery. IEEE J. Solid State Circuits 44(11): 3120-3130 (2009) - [j12]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 609-622 (2009) - [j11]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram:
A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1612-1621 (2009) - 2008
- [j10]Pavan Kumar Hanumolu, Volodymyr Kratyuk, Gu-Yeon Wei, Un-Ku Moon:
A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter. IEEE J. Solid State Circuits 43(2): 414-424 (2008) - [j9]Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon:
A Wide-Tracking Range Clock and Data Recovery Circuit. IEEE J. Solid State Circuits 43(2): 425-439 (2008) - [j8]Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon:
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. IEEE J. Solid State Circuits 43(5): 1195-1206 (2008) - [j7]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity Analysis for Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1521-1534 (2008) - 2007
- [j6]Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters. IEEE J. Solid State Circuits 42(8): 1699-1709 (2007) - [j5]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 247-251 (2007) - 2006
- [j4]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. IEEE J. Solid State Circuits 41(12): 2720-2728 (2006) - 2005
- [j3]Gowtham Vemulapalli, Pavan Kumar Hanumolu, Youn-Jae Kook, Un-Ku Moon:
A 0.8-V accurately tuned linear continuous-time filter. IEEE J. Solid State Circuits 40(9): 1972-1977 (2005) - 2004
- [j2]Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon:
Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(9): 1665-1674 (2004) - 2003
- [j1]Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon:
Analysis of PLL clock jitter in high-speed serial links. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 879-886 (2003)
Conference and Workshop Papers
- 2024
- [c104]Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu:
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. ISSCC 2024: 138-140 - 2023
- [c103]Saion K. Roy, Han-Mo Ou, Mostafa Gamal Ahmed, Peter Deaville, Bonan Zhang, Naveen Verma, Pavan Kumar Hanumolu, Naresh R. Shanbhag:
Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation. ESSCIRC 2023: 25-28 - [c102]Kyu-Sang Park, Nilanjan Pal, Yongxin Li, Ruhao Xia, Tianyu Wang, Ahmed E. AbdelRahman, Pavan Kumar Hanumolu:
A $1.4\mu$ W/MHz 100MHz RC Oscillator with $\pm$ 1030ppm Inaccuracy from $-40^{\circ}\mathrm{C}$ to $85^{\circ}\mathrm{C}$ After Accelerated Aging for 500 Hours at $125^{\circ}\mathrm{C}$. ISSCC 2023: 62-63 - [c101]Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu:
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. ISSCC 2023: 206-207 - [c100]Ahmed E. AbdelRahman, Mostafa Gamal Ahmed, Mahmoud A. Khalil, Mohamed Badr Younis, Kyu-Sang Park, Pavan Kumar Hanumolu:
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. ISSCC 2023: 208-209 - [c99]Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu:
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c98]Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu:
High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS 2022: 9-16 - [c97]Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, Pavan Kumar Hanumolu:
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. CICC 2022: 1-2 - 2021
- [c96]Ahmed Elmallah, Junheng Zhu, Amr Khashaba, Karim M. Megawer, Ahmed Elkholy, Pavan Kumar Hanumolu:
A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction. CICC 2021: 1-2 - [c95]Kyu-Sang Park, Amr Khashaba, Ahmed E. AbdelRahman, Yongxin Li, Tianyu Wang, Ruhao Xia, Nilanjan Pal, Pavan Kumar Hanumolu:
A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C. CICC 2021: 1-2 - 2020
- [c94]Nilanjan Pal, Adam Fish, William McIntyre, Nathanael Griesert, Greg Winter, Travis Eichhorn, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS. CICC 2020: 1-4 - [c93]Amr Khashaba, Junheng Zhu, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
3.2 A 0.0088mm2 Resistor-Based Temperature Sensor Achieving 92fJ·K2 FoM in 65nm CMOS. ISSCC 2020: 60-62 - [c92]Amr Khashaba, Junheng Zhu, Mostafa Gamal Ahmed, Nilanjan Pal, Pavan Kumar Hanumolu:
3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors. ISSCC 2020: 66-68 - 2019
- [c91]Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer. CICC 2019: 1-4 - [c90]Karim M. Megawer, Nilanjan Pal, Ahmed Elkholy, Mostafa Gamal Ahmed, Amr Khashaba, Danielle Griffith, Pavan Kumar Hanumolu:
A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS. ISSCC 2019: 302-304 - 2018
- [c89]Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS. CICC 2018: 1-4 - [c88]Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu:
A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR. CICC 2018: 1-4 - [c87]Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar:
Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA 2018: 561-574 - [c86]Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony:
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. ISSCC 2018: 388-389 - [c85]Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu:
A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS. ISSCC 2018: 392-394 - [c84]Qadeer Ahmad Khan, Seong Joong Kim, Pavan Kumar Hanumolu:
Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers. VLSID 2018: 226-231 - 2017
- [c83]Pavan Kumar Hanumolu:
Time-based ΑΣADCs. CICC 2017: 1-44 - [c82]Seong Joong Kim, Woo-Seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes. CICC 2017: 1-4 - [c81]Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC 2017: 1-4 - [c80]Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu:
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC 2017: 1-4 - [c79]Xun Jian, Pavan Kumar Hanumolu, Rakesh Kumar:
Understanding and Optimizing Power Consumption in Memory Networks. HPCA 2017: 229-240 - [c78]Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu:
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC 2017: 152-153 - [c77]Wen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski:
10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS. ISSCC 2017: 182-183 - [c76]Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu:
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC 2017: 492-493 - [c75]Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - [c74]Ichiro Fujimori, Pavan Kumar Hanumolu:
EE4: Semiconductor economics: How business decisions are engineered. ISSCC 2017: 523 - 2016
- [c73]Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu:
10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. ISSCC 2016: 192-193 - [c72]Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu:
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. ISSCC 2016: 338-340 - [c71]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu:
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC 2016: 398-399 - [c70]Ichiro Fujimori, Martin Brox, Elad Alon, Pavan Kumar Hanumolu, Gerrit den Besten, Hideyuki Nosaka:
F4: Emerging short-reach and high-density interconnect solutions for internet of everything. ISSCC 2016: 502-505 - 2015
- [c69]Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu:
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC 2015: 1-4 - [c68]Pavan Kumar Hanumolu:
Low dropout regulators. CICC 2015: 1-37 - [c67]Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC 2015: 1-3 - [c66]Woo-Seok Choi, Guanghua Shu, Mrunmay Talegaonkar, Yubo Liu, Da Wei, Luca Benini, Pavan Kumar Hanumolu:
3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS. ISSCC 2015: 1-3 - [c65]Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu:
10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. ISSCC 2015: 1-3 - [c64]Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu:
12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm2 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. ISSCC 2015: 1-3 - [c63]Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu:
A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS. VLSIC 2015: 200- - [c62]Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu:
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC 2015: 256- - [c61]Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC 2015: 352- - 2014
- [c60]Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu:
A VCO-based current-to-digital converter for sensor applications. CICC 2014: 1-4 - [c59]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu:
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC 2014: 150-151 - [c58]Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu:
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC 2014: 272-273 - [c57]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC 2014: 1-2 - [c56]Qadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW. VLSIC 2014: 1-2 - [c55]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC 2014: 1-2 - [c54]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC 2014: 1-2 - [c53]Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu:
A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. VLSIC 2014: 1-2 - 2013
- [c52]Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu:
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC 2013: 1-4 - [c51]Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC 2013: 256-257 - 2012
- [c50]Tao Tong, Wenhuan Yu, Pavan Kumar Hanumolu, Gabor C. Temes:
Calibration technique for SAR analog-to-digital converters. ISCAS 2012: 2993-2996 - [c49]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154 - [c48]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC 2012: 242-244 - [c47]Brian Drost, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4th-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS. ISSCC 2012: 360-362 - [c46]Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC 2012: 464-466 - [c45]Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu:
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. VLSIC 2012: 182-183 - [c44]Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC 2012: 188-189 - [c43]Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez:
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design 2012: 20-21 - 2011
- [c42]Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
Area efficient phase calibration of a 1.6 GHz multiphase DLL. CICC 2011: 1-4 - [c41]Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez:
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC 2011: 1-4 - [c40]Sanghyeon Lee, Jeongseok Chae, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes:
A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. CICC 2011: 1-4 - [c39]Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu:
Digital clock and data recovery circuit design: Challenges and tradeoffs. CICC 2011: 1-8 - [c38]Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu:
A high-PSR LDO using a feedforward supply-noise cancellation technique. CICC 2011: 1-4 - [c37]Qadeer Khan, Sachin Rao, Damian Swank, Arun Rao, William McIntyre, Sarvesh Bang, Pavan Kumar Hanumolu:
A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control. ESSCIRC 2011: 439-442 - [c36]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC 2011: 92-94 - [c35]Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154 - [c34]Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu:
A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing. ISSCC 2011: 238-240 - [c33]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC 2011: 438-450 - [c32]Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu:
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC 2011: 440-442 - 2010
- [c31]Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Qadeer Khan, Pavan Kumar Hanumolu:
A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction. CICC 2010: 1-4 - [c30]Jeongseok Chae, Sanghyeon Lee, Mitsuru Aniya, Seiji Takeuchi, Koichi Hamashita, Pavan Kumar Hanumolu, Gabor C. Temes:
A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. CICC 2010: 1-4 - [c29]Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu:
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. CICC 2010: 1-4 - [c28]Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu:
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC 2010: 1-4 - 2009
- [c27]Sunwoo Kwon, Pavan Kumar Hanumolu, Sang-Ho Kim, Sung-No Lee, Seung-Bin You, Ho-Jin Park, Jae-Whui Kim, Un-Ku Moon:
An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. CICC 2009: 171-174 - [c26]David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC with inherent anti-alias filtering. CICC 2009: 275-278 - [c25]Pavan Kumar Hanumolu, Alessandro Piovaccari:
Over-sampled data converters. CICC 2009 - [c24]Skyler Weaver, Benjamin P. Hershberg, Pavan Kumar Hanumolu, Un-Ku Moon:
A multiplexer-based digital passive linear counter (PLINCO). ICECS 2009: 607-610 - 2008
- [c23]David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un-Ku Moon:
A continuous-time input pipeline ADC. CICC 2008: 169-172 - [c22]Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu:
A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB. CICC 2008: 443-446 - [c21]Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction. CICC 2008: 459-462 - [c20]Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Noise tolerant oscillator design using perturbation projection vector analysis. CICC 2008: 695-698 - [c19]Peter Kurahashi, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V downconversion filter using duty-cycle controlled bandwidth tuning. CICC 2008: 707-710 - [c18]Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE 2008: 312-317 - [c17]Abhijith Arakali, Nema Talebbeydokthi, Srikanth Gondi, Pavan Kumar Hanumolu:
Supply-noise mitigation techniques in phase-locked loops. ESSCIRC 2008: 374-377 - [c16]Ankur Agrawal, Pavan Kumar Hanumolu, Gu-Yeon Wei:
An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery. ISSCC 2008: 468-469 - 2007
- [c15]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. CICC 2007: 305-308 - [c14]Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V 10b 30MSPS Switched-RC Pipelined ADC. CICC 2007: 325-328 - [c13]Merrick Brownlee, Pavan Kumar Hanumolu, Un-Ku Moon:
A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance. CICC 2007: 353-356 - [c12]Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram:
Digitally-Enhanced Phase-Locking Circuits. CICC 2007: 361-368 - [c11]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC 2007: 547-550 - [c10]Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Sensitivity analysis for oscillators. ICCAD 2007: 458-463 - [c9]Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. ICECS 2007: 494-497 - 2006
- [c8]Pavan Kumar Hanumolu, Min-Gyu Kim, Gu-Yeon Wei, Un-Ku Moon:
A 1.6Gbps Digital Clock and Data Recovery Circuit. CICC 2006: 603-606 - [c7]Peter Kurahashi, Pavan Kumar Hanumolu, Gabor C. Temes, Un-Ku Moon:
A 0.6V Highly Linear Switched-R-MOSFET-C Filter. CICC 2006: 833-836 - [c6]Nasser Talebbeydokhti, Pavan Kumar Hanumolu, Peter Kurahashi, Un-Ku Moon:
Constant transconductance bias circuit with an on-chip resistor. ISCAS 2006 - [c5]Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. ISSCC 2006: 2412-2421 - 2005
- [c4]Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
A low spur fractional-N frequency synthesizer architecture. ISCAS (3) 2005: 2807-2810 - [c3]Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) 2005: 3986-3989 - 2004
- [c2]Gowtham Vemulapalli, Pavan Kumar Hanumolu, Un-Ku Moon:
A 0.8V accurately-tuned continuous-time filter. CICC 2004: 45-48 - [c1]Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei, Un-Ku Moon:
Jitter in high-speed serial and parallel links. ISCAS (4) 2004: 425-428
Informal and Other Publications
- 2018
- [i1]Or Ordentlich, Gizem Tabak, Pavan Kumar Hanumolu, Andrew C. Singer, Gregory W. Wornell:
A Modulo-Based Architecture for Analog-to-Digital Conversion. CoRR abs/1806.08968 (2018)
Coauthor Index
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