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2020 – today
- 2023
[c11]Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx:
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC 2023: 74-75- 2021
- [j6]Meng Li
, Veerle Derudder, Kaoutar Bertrand, Claude Desset, André Bourdoux:
High-Speed LDPC Decoders Towards 1 Tb/s. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2224-2233 (2021) - 2020
- [i1]Altug Süral, E. Göksu Sezer, Ertugrul Kolagasioglu, Veerle Derudder, Kaoutar Bertrand:
Tb/s Polar Successive Cancellation Decoder 16nm ASIC Implementation. CoRR abs/2009.09388 (2020)
2010 – 2019
- 2018
- [c10]Meng Li, Veerle Derudder, Claude Desset, Andy Dewilde, André Bourdoux, Yanxiang Huang:
A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard. ISTC 2018: 1-5 - 2017
- [j5]Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo:
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2613-2626 (2017) - 2016
- [c9]Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo:
A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS. A-SSCC 2016: 105-108 - 2015
- [c8]Meng Li, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre, Wim Van Thillo:
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. A-SSCC 2015: 1-5
2000 – 2009
- 2007
- [c7]Bruno Bougard, André Bourdoux, Frederik Naessens, Miguel Glassee, Veerle Derudder, Liesbet Van der Perre:
Energy-efficient software-defined radio solutions for MIMO-based broadband communication. EUSIPCO 2007: 1141-1145 - 2006
- [j4]Jan-Willem Weijers, Veerle Derudder, Sven Janssens, Frederik Petré, André Bourdoux:
From MIMO-OFDM Algorithms to a Real-Time Wireless Prototype: A Systematic Matlab-to-Hardware Design Flow. EURASIP J. Adv. Signal Process. 2006 (2006) - [c6]Thomas Schuster, D. N. Bruna, Bruno Bougard, Veerle Derudder, A. Hoffmann, Liesbet Van der Perre:
Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio. SiPS 2006: 351-356 - 2004
- [c5]Maryse Wouters, André Bourdoux, Stefaan De Rore, Sven Janssens, Veerle Derudder:
An approach for real time prototyping of MIMO-OFDM systems. EUSIPCO 2004: 689-692 - 2003
- [j3]Bruno Bougard, Liesbet Van der Perre, F. Maessen, Alexandre Giulietti, Veerle Derudder, Francky Catthoor:
Memory Power Reduction for High-Speed Implementation of Turbo Codes. J. VLSI Signal Process. 33(3): 307-316 (2003) - [c4]Andrew Fort, Jan-Willem Weijers, Veerle Derudder, Wolfgang Eberle, André Bourdoux:
A performance and complexity comparison of auto-correlation and cross-correlation for OFDM burst synchronization. ICASSP (2) 2003: 341-344 - 2002
- [c3]Alexandre Giulietti, Bruno Bougard, Veerle Derudder, Steven Dupont, Jan-Willem Weijers, Liesbet Van der Perre:
A 80 Mb/s low-power scalable turbo codec core. CICC 2002: 389-392 - 2001
- [j2]Wolfgang Eberle, Veerle Derudder, Geert Vanwijnsberghe, Mario Vergara, Luc Deneire, Liesbet Van der Perre, Marc Engels, Ivo Bolsens, Hugo De Man:
80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band. IEEE J. Solid State Circuits 36(11): 1829-1838 (2001)
1990 – 1999
- 1999
- [j1]Robert Pasko, Patrick Schaumont, Veerle Derudder, Serge Vernalde, Daniela Duracková:
A new algorithm for elimination of common subexpressions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(1): 58-68 (1999) - 1997
- [c2]Robert Pasko, Patrick Schaumont, Veerle Derudder, Daniela Duracková:
Optimization Method for Broadband Modem FIR Filter Design using Common Subexpression Elimination. ISSS 1997: 100-106 - 1992
- [c1]Evagelos Katsadas, Zohair Sahraoui, Maryse Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man:
Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. Synthesis for Control Dominated Circuits 1992: 167-181
Coauthor Index
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