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2020 – today
- 2020
[c37]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. MLSys 2020
2010 – 2019
- 2019
- [j9]Keith A. Campbell
, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen:
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1345-1358 (2019) - [c36]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen:
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. DAC 2019: 206 - [i3]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen:
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. CoRR abs/1904.04421 (2019) - [i2]Xiaofan Zhang, Cong Hao, Haoming Lu, Jiachen Li, Yuhong Li, Yuchen Fan, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection. CoRR abs/1906.10327 (2019) - [i1]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-mei W. Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. CoRR abs/1909.09709 (2019) - 2017
- [c35]Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FPGA 2017: 275-284 - [c34]Xiaofan Zhang, Xinheng Liu, Anand Ramachandran, Chuanhao Zhuge, Shibin Tang, Peng Ouyang, Zuofu Cheng, Kyle Rupnow, Deming Chen:
High-performance video content recognition with long-term recurrent convolutional network for FPGA. FPL 2017: 1-4 - [c33]Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. ICCAD 2017: 819-826 - [c32]Xiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen:
Machine learning on FPGAs to face the IoT revolution. ICCAD 2017: 894-901 - 2016
- [j8]Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang:
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 70-77 (2016) - [j7]Yun Liang, Muhammad Teguh Satria, Kyle Rupnow, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1165-1178 (2016) - [j6]Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [j5]Yao Chen, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow, Deming Chen:
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2220-2233 (2016) - [c31]Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen:
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. ASP-DAC 2016: 218-225 - [c30]Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. DAC 2016: 7:1-7:6 - [c29]Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen:
Real-time system-level implementation of a telepresence robot using an embedded GPU platform. DATE 2016: 1445-1448 - [c28]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. FCCM 2016: 127-130 - [c27]Gowthami Jayashri Manikandan, Sitao Huang, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. FCCM 2016: 137 - [c26]Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. FPGA 2016: 5-14 - [c25]Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
High Level Synthesis of Complex Applications: An H.264 Video Decoder. FPGA 2016: 224-233 - [c24]Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). FPGA 2016: 278 - [c23]Tan Nguyen, Yao Chen, Kyle Rupnow, Swathi T. Gurumani, Deming Chen:
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. ISVLSI 2016: 661-666 - 2015
- [j4]Yun Liang, Huynh Phung Huynh, Kyle Rupnow, Rick Siow Mong Goh, Deming Chen:
Efficient GPU Spatial-Temporal Multitasking. IEEE Trans. Parallel Distributed Syst. 26(3): 748-760 (2015) - [c22]Liwei Yang, Yao Chen, Wei Zuo, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
System-level design solutions: Enabling the IoT explosion. ASICON 2015: 1-4 - [c21]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
Behavioral-level IP integration in high-level synthesis. FPT 2015: 172-175 - [c20]Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
JIT trace-based verification for high-level synthesis. FPT 2015: 228-231 - 2014
- [j3]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow:
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1832-1845 (2014) - [c19]Swathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen:
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM 2014: 21-24 - [c18]Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Fast and effective placement and routing directed high-level synthesis for FPGAs. FPGA 2014: 1-10 - [c17]Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
New solutions for system-level and high-level synthesis (Invited paper). ISIC 2014: 71-74 - 2013
- [c16]Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen:
High-level synthesis of multiple dependent CUDA kernels on FPGA. ASP-DAC 2013: 305-312 - [c15]Yun Liang, Zheng Cui, Kyle Rupnow, Deming Chen:
Register and thread structure optimization for GPUs. ASP-DAC 2013: 461-466 - [c14]Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong:
Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA 2013: 9-18 - [c13]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow:
High-level synthesis with behavioral level multi-cycle path analysis. FPL 2013: 1-8 - 2012
- [j2]Yun Liang, Kyle Rupnow, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen:
High-Level Synthesis: Productivity, Performance, and Software Constraints. J. Electr. Comput. Eng. 2012: 649057:1-649057:14 (2012) - [c12]Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen:
Real-time implementation and performance optimization of 3D sound localization on GPUs. DATE 2012: 832-835 - [c11]Zheng Cui, Yun Liang, Kyle Rupnow, Deming Chen:
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. IPDPS 2012: 83-94 - 2011
- [j1]Kyle Rupnow, Keith D. Underwood, Katherine Compton:
Scientific Application Demands on a Reconfigurable Functional Unit Interface. ACM Trans. Reconfigurable Technol. Syst. 4(2): 19:1-19:30 (2011) - [c10]Kyle Rupnow, Yun Liang, Yinan Li, Deming Chen:
A study of high-level synthesis: Promises and challenges. ASICON 2011: 1102-1105 - [c9]Kyle Rupnow, Yun Liang, Yinan Li, Dongbo Min, Minh N. Do, Deming Chen:
High level synthesis of stereo matching: Productivity, performance, and software constraints. FPT 2011: 1-8 - 2010
- [c8]Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton:
Accurately evaluating application performance in simulated hybrid multi-tasking systems. FPGA 2010: 135-144 - [c7]Philip Garcia, Kyle Rupnow, Katherine Compton:
A Reconfigurable Computing Scheduler Optimized for Multicore Systems. FPL 2010: 107-112 - [c6]Hsiang-Kuo Tang, Kyle Rupnow, Parmesh Ramanathan, Katherine Compton:
Dynamic Binding and Scheduling of Firm-Deadline Tasks on Heterogeneous Compute Resources. RTCSA 2010: 275-280
2000 – 2009
- 2009
- [c5]Kyle Rupnow, Wenyin Fu, Katherine Compton:
Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking. FCCM 2009: 63-70 - [c4]Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton:
Performance metrics for hybrid multi-tasking systems. FPL 2009: 547-550 - 2007
- [c3]Kyle Rupnow, Keith D. Underwood, Katherine Compton:
Scientific Application Acceleration with Reconfigurable Functional Units. FCCM 2007: 261-274 - [c2]Jonathan Evans, Kyle Rupnow, Katherine Compton:
Reconfigurable Functional Units for Scientific Superscalar Processors. FPT 2007: 73-80 - 2006
- [c1]Kyle Rupnow, Arun Rodrigues, Keith D. Underwood, Katherine Compton:
Scientific applications vs. SPEC-FP: a comparison of program behavior. ICS 2006: 66-74
Coauthor Index
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