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2020 – today
- 2024
[j21]David M. Harris
, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek:
Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers 73(1): 292-300 (2024)- 2023
- [j20]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò:
An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access 11: 98586-98595 (2023) - [c55]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re:
Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC 2023: 1547-1551 - 2022
- [j19]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re:
Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. 10(1): 186-198 (2022) - [j18]Stuart F. Oberman, Leonel Sousa, Bogdan Pasca, Alberto Nannarelli:
Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic. IEEE Trans. Emerg. Top. Comput. 10(3): 1239-1240 (2022) - 2021
- [j17]Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò:
M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1912-1916 (2021) - [j16]Hong-Ning Dai Senior, Zibin Zheng, Yan Zhang, Michael Rung-Tsong Lyu, Alberto Nannarelli:
Special Section on Scalable Computing for Blockchain Systems. IEEE Trans. Emerg. Top. Comput. 9(3): 1372 (2021) - [j15]Mioara Joldes, Fabrizio Lamberti, Alberto Nannarelli:
Special Section on "Emerging and Impacting Trends on Computer Arithmetic". IEEE Trans. Emerg. Top. Comput. 9(3): 1449-1450 (2021) - 2020
- [j14]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò:
N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 565-569 (2020) - [c54]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò:
FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC 2020: 116-120 - [c53]Alberto Nannarelli:
Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors. ARITH 2020: 96-102
2010 – 2019
- 2019
- [j13]Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò:
A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access 7: 124147-124157 (2019) - [j12]Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re:
An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access 7: 186340-186351 (2019) - [j11]Alberto Nannarelli:
Tunable Floating-Point Adder. IEEE Trans. Computers 68(10): 1553-1560 (2019) - [c52]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC 2019: 1616-1620 - [c51]L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Digital Signal Processing Accelerator for RISC-V. ICECS 2019: 703-706 - [c50]Alberto Nannarelli:
Fused Multiply-Add for Variable Precision Floating-Point. SoCC 2019: 342-347 - 2018
- [c49]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC 2018: 199-202 - [c48]Alberto Nannarelli:
Tunable Floating-Point for Energy Efficient Accelerators. ARITH 2018: 29-36 - [c47]Marta Franceschi, Alberto Nannarelli, Maurizio Valle:
Tunable Floating-Point for Artificial Neural Networks. ICECS 2018: 289-292 - [c46]Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò:
Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD 2018: 1-20 - [c45]Marta Franceschi, Alberto Nannarelli, Maurizio Valle:
Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation. SMACD 2018: 89-92 - 2017
- [j10]Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli:
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 409-418 (2017) - [c44]Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari:
Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC 2017: 86-90 - [c43]Alberto Nannarelli:
A multi-format floating-point multiplier for power-efficient operations. SoCC 2017: 351-356 - 2016
- [j9]Alberto Nannarelli:
Performance/Power Space Exploration for Binary64 Division Units. IEEE Trans. Computers 65(5): 1671-1677 (2016) - [c42]A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re:
Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC 2016: 882-886 - [c41]Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
A hardware framework for on-chip FPGA acceleration. ISIC 2016: 1-4 - [c40]Jonathan Taylor, Alberto Nannarelli:
Design and simulation of a quaternary memory cell based on a physical memristor. NORCAS 2016: 1-6 - 2015
- [j8]Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula:
Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems 39(8): 807-815 (2015) - [c39]Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re:
A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT 2015: 291-296 - [c38]Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Characterization of RNS multiply-add units for power efficient DSP. MWSCAS 2015: 1-4 - [r1]Wei Liu, Alberto Nannarelli:
Power and Thermal Efficient Numerical Processing. Handbook on Data Centers 2015: 263-286 - 2014
- [j7]Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang:
Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers 63(8): 1852-1853 (2014) - [c37]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC 2014: 436-439 - [c36]Jakob Kenn Toft, Alberto Nannarelli:
Energy efficient FPGA based hardware accelerators for financial applications. NORCHIP 2014: 1-6 - [c35]Alberto Nannarelli:
Decimal engine for energy-efficient multicore processors. VLSI-SoC 2014: 1-6 - 2013
- [j6]Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino:
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 406-418 (2013) - [c34]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC 2013: 2172-2176 - [e1]Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang:
21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-5644-2 [contents] - 2012
- [j5]Tomás Lang, Alberto Nannarelli:
Comments on 'improving the speed of decimal division'. IET Comput. Digit. Tech. 6(6): 370-371 (2012) - [j4]Wei Liu, Alberto Nannarelli:
Power Efficient Division and Square Root Unit. IEEE Trans. Computers 61(8): 1059-1070 (2012) - [c33]Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re:
Imprecise arithmetic for low power image processing. ACSCC 2012: 983-987 - [c32]Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Power efficient design of parallel/serial FIR filters in RNS. ACSCC 2012: 1015-1019 - [c31]Jonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli:
Design of power efficient FPGA based hardware accelerators for financial applications. NORCHIP 2012: 1-4 - 2011
- [c30]Alberto Nannarelli:
Radix-16 Combined Division and Square Root Unit. IEEE Symposium on Computer Arithmetic 2011: 169-176 - [c29]Nicolas Borup, Jonas Dindorp, Alberto Nannarelli:
FPGA implementation of decimal processors for hardware acceleration. NORCHIP 2011: 1-4 - [c28]Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula:
Temperature dependent wire delay estimation in floorplanning. NORCHIP 2011: 1-4 - [c27]Alberto Nannarelli:
FPGA Based Acceleration of Decimal Operations. ReConFig 2011: 146-151 - 2010
- [c26]Wei Liu, Alberto Nannarelli:
Power dissipation challenges in multicore floating-point units. ASAP 2010: 257-264 - [c25]Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino:
Post-placement temperature reduction techniques. DATE 2010: 634-637
2000 – 2009
- 2009
- [c24]Tomás Lang, Alberto Nannarelli:
Division Unit for Binary Integer Decimals. ASAP 2009: 1-7 - [c23]Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino:
On-chip Thermal Modeling Based on SPICE Simulation. PATMOS 2009: 66-75 - 2008
- [c22]Alberto Nannarelli:
Session TP8b1: Computer arithmetic II. ACSCC 2008: 1782-1784 - [c21]Wei Liu, Alberto Nannarelli:
Power dissipation in division. ACSCC 2008: 1790-1794 - [c20]Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
Reducing power dissipation in pipelined accumulators. ACSCC 2008: 2098-2102 - [c19]Luigi Dadda, Alberto Nannarelli:
A variant of a radix-10 combinational multiplier. ISCAS 2008: 3370-3373 - [c18]Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli:
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS 2008: 3434-3437 - [c17]Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re:
On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) 2008: 174-190 - 2007
- [j3]Tomás Lang, Alberto Nannarelli:
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. IEEE Trans. Computers 56(6): 727-739 (2007) - [c16]G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Low-power adaptive filter based on RNS components. ISCAS 2007: 3211-3214 - 2005
- [j2]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers 54(7): 837-851 (2005) - [c15]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic 2005: 147-154 - [c14]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) 2005: 1102-1105 - 2004
- [c13]Andrea Del Re, Alberto Nannarelli, Marco Re:
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. DATE 2004: 686-687 - [c12]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) 2004: 725-728 - 2003
- [c11]Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re:
Power-delay tradeoffs in residue number system. ISCAS (5) 2003: 413-416 - 2002
- [c10]Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP 2002: 185-196 - [c9]Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re:
Power characterization of digital filters implemented on FPGA. ISCAS (5) 2002: 801-804 - 2001
- [c8]Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli:
Tradeoffs between residue number system and traditional FIR filters. ISCAS (2) 2001: 305-308 - [c7]Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture. ISCAS (4) 2001: 350-353 - [c6]Luca Benini, Alberto Macii, Alberto Nannarelli:
Cached-code compression for energy minimization in embedded processors. ISLPED 2001: 322-327
1990 – 1999
- 1999
- [j1]Alberto Nannarelli, Tomás Lang:
Low-Power Divider. IEEE Trans. Computers 48(1): 2-14 (1999) - [c5]Alberto Nannarelli, Tomás Lang:
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. IEEE Symposium on Computer Arithmetic 1999: 60- - [c4]Alberto Nannarelli, Tomás Lang:
Low-Power Radix-4 Combined Division and Square Root. ICCD 1999: 236-242 - 1998
- [c3]Alberto Nannarelli, Tomás Lang:
Low-power radix-8 divider. ICCD 1998: 420-426 - [c2]Alberto Nannarelli, Tomás Lang:
Power-delay tradeoffs for radix-4 and radix-8 dividers. ISLPED 1998: 109-111 - 1996
- [c1]Alberto Nannarelli, Tomás Lang:
Low-power radix-4 divider. ISLPED 1996: 205-208
Coauthor Index
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