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2010 – 2019
- 2018
[j58]Pin-Chen Kuo
, Kuan-Lun Lo, Huan-Kai Tseng, Kuan-Ting Lee, Bin-Da Liu, Jar-Ferr Yang:
Stereoview to Multiview Conversion Architecture for Auto-Stereoscopic 3D Displays. IEEE Trans. Circuits Syst. Video Technol. 28(11): 3274-3287 (2018)- 2017
- [j57]Tse-An Chen, Wen-Jui Wu, Chia-Ling Wei, Robert B. Darling, Bin-Da Liu:
Novel 10-Bit Impedance-to-Digital Converter for Electrochemical Impedance Spectroscopy Measurements. IEEE Trans. Biomed. Circuits Syst. 11(2): 370-379 (2017) - [j56]I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting:
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 621-634 (2017) - 2016
- [j55]Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen, Hong-Tzer Yang:
New Power Factor Correction Application for a Small Wind Power System. IEICE Trans. Electron. 99-C(5): 581-589 (2016) - [j54]Wei-Chiun Liu, Bin-Da Liu, Chia-Ling Wei:
A Multi-Channel Electrochemical Measurement System for Biomolecular Detection. IEICE Trans. Electron. 99-C(11): 1295-1303 (2016) - [j53]Mikhail K. Tchobanou, Bin-Da Liu:
Special issue on Efficient video coding and beyond. Multidimens. Syst. Signal Process. 27(3): 619-621 (2016) - [j52]Pin-Chen Kuo, Jhih-Ming Lin, Bin-Da Liu, Jar-Ferr Yang:
High efficiency depth image-based rendering with simplified inpainting-based hole filling. Multidimens. Syst. Signal Process. 27(3): 623-645 (2016) - [c57]Pin-Chen Kuo, Kuan-Ting Lee, Ching-Lun Chou, Chun-Wei Chang, Bin-Da Liu, Jar-Ferr Yang:
An advanced 3D format generation architecture for video and depth. APCCAS 2016: 654-657 - [c56]Tse-An Chen, Chia-Ling Wei, Bin-Da Liu:
Comparative frequency response analysis system for electrochemical impedance spectroscopy measurements. EMBC 2016: 1910-1913 - 2015
- [j51]Chi-Kun Lin, Yi-Hsien Wu, Jar-Ferr Yang, Bin-Da Liu:
An iterative enhanced super-resolution system with edge-dominated interpolation and adaptive enhancements. EURASIP J. Adv. Signal Process. 2015: 9 (2015) - [j50]Pin-Chen Kuo, Kuan-Hsing Lu, Yun-Ning Hsu, Bin-Da Liu, Jar-Ferr Yang:
Fast three-dimensional video coding encoding algorithms based on edge information of depth map. IET Image Process. 9(7): 587-595 (2015) - [j49]Pin-Chen Kuo, An-Jie Lin, Bin-Da Liu, Jar-Ferr Yang:
An Advanced Video and Depth Depacking Architecture for 3D Applications. J. Inf. Sci. Eng. 31(5): 1537-1555 (2015) - [c55]Po-Chang Wu, Bin-Da Liu, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang:
Design of a 0.6-V 0.2-mW CMOS MEMS accelerometer. ICCE-TW 2015: 444-445 - 2014
- [j48]I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang:
A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder. IEICE Trans. Electron. 97-C(6): 526-537 (2014) - [j47]Shih-Tse Wei, Pin-Chen Kuo, Bin-Da Liu, Jar-Ferr Yang:
Efficient residual coding algorithm based on hadamard transform in lossless H.264/AVC. IET Image Process. 8(4): 191-198 (2014) - [j46]Chia-Ling Wei, Yi-Wen Wang, Bin-Da Liu:
Wide-Range Filter-Based Sinusoidal Wave Synthesizer for Electrochemical Impedance Spectroscopy Measurements. IEEE Trans. Biomed. Circuits Syst. 8(3): 442-450 (2014) - [j45]Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu:
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 879-892 (2014) - [c54]Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen, Hong-Tzer Yang:
A low supply voltage mixed-signal maximum power point tracking controller for photovoltaic power system. SoCC 2014: 125-129 - 2013
- [j44]Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen:
A Simple Implementation of Nonlinear-Carrier Control for Power Factor Correction Rectifier With Variable Slope Ramp on Field-Programmable Gate Array. IEEE Trans. Ind. Informatics 9(3): 1322-1329 (2013) - [c53]Pin-Chen Kuo, Jhih-Ming Lin, Bin-Da Liu, Jar-Ferr Yang:
Inpainting-based multi-view synthesis algorithms and its GPU accelerated implementation. ICICS 2013: 1-4 - [c52]Jr-Fu Yang, Chia-Ling Wei, Jian-Fu Wu, Bin-Da Liu:
Design of a dual-mode electrochemical measurement and analysis system. EMBC 2013: 3265-3268 - [c51]I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, Soon-Jyh Chang:
A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique. ISCAS 2013: 2002-2005 - [c50]Po-Chang Wu, Bin-Da Liu, Yu-Chen Teng, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang:
Novel automatic offset cancellation approach for capacitive CMOS MEMS accelerometers. ISCE 2013: 147-148 - 2012
- [j43]I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting:
A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing. IEICE Trans. Electron. 95-C(11): 1799-1809 (2012) - [c49]Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu:
Performance-driven analog placement considering monotonic current paths. ICCAD 2012: 613-619 - 2011
- [j42]Yuan-Ta Hsieh, Bin-Da Liu, Jian-Fu Wu, Chiao-Li Fang, Hann-Huei Tsai, Ying-Zong Juang:
A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 244-248 (2011) - [j41]Hsieh-Wei Lee, King-Chu Hung, Bin-Da Liu, Sheau-Fang Lei, Hsin-Wen Ting:
Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1287-1299 (2011) - [j40]Shih-Tse Wei, Chia-Wei Tien, Bin-Da Liu, Jar-Ferr Yang:
Adaptive Truncation Algorithm for Hadamard-Transformed H.264/AVC Lossless Video Coding. IEEE Trans. Circuits Syst. Video Technol. 21(5): 538-549 (2011) - [j39]Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu:
A Two-Stage Rate Control Mechanism for RDO-Based H.264/AVC Encoders. IEEE Trans. Circuits Syst. Video Technol. 21(5): 660-673 (2011) - [c48]Shih-Chang Chang, I-Jen Chao, Bin-Da Liu, Chun-Yueh Huang, Mei-Hwa Lee, Hung-Yin Lin:
Design of a signal processing circuit for quartz crystal microbalance biosensors. ASICON 2011: 180-183 - [c47]Chen-Hsin Hsieh, Hung-Yin Lin, Chien-Fu Lin, Hann-Huei Tsai, Ying-Zong Juang, Chun-Yueh Huang, Bin-Da Liu, Mei-Hwa Lee:
A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-c0-vinyl alcohol) based electrode. NEMS 2011: 575-578 - [c46]Chen-Hsin Hsieh, Hung-Yin Lin, Chun-Yueh Huang, Chien-Fu Lin, Hann-Huei Tsai, Ying-Zong Juang, Bin-Da Liu, Mei-Hwa Lee:
A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-co-vinyl alcohol) based electrode. NEMS 2011: 711-714 - 2010
- [j38]Karunanithi Bharanitharan, Bin-Da Liu, Jar-Ferr Yang:
Classified Region Algorithm for Fast Intermode Decision in H.264/AVC Encoder. EURASIP J. Adv. Signal Process. 2010 (2010) - [j37]Chih-Hung Kuo, Li-Chuan Chang, Kuan-Wei Fan, Bin-Da Liu:
Hardware/Software Codesign of a Low-Cost Rate Control Scheme for H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 20(2): 250-261 (2010) - [j36]Heng-Yao Lin, Kuan-Hsien Wu, Bin-Da Liu, Jar-Ferr Yang:
An Efficient VLSI Architecture for Transform-Based Intra Prediction in H.264/AVC. IEEE Trans. Circuits Syst. Video Technol. 20(6): 894-906 (2010) - [c45]Yuan-Ta Hsieh, Bin-Da Liu, Jian-Fu Wu, Chiao-Li Fang, Hann-Huei Tsai, Ying-Zong Juang:
A high efficiency boost white LED driver with an integrated Schottky diode. APCCAS 2010: 660-663 - [c44]Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu:
Low complexity MAD prediction algorithms for rate controllable H.264/AVC hardware encoders. ISCAS 2010: 661-664
2000 – 2009
- 2009
- [j35]Hsieh-Wei Lee, Bin-Da Liu, King-Chu Hung, Sheau-Fang Lei, Po-Chin Wang, Tsung-Lung Yang:
Breast Tumor Classification of Ultrasound Images Using Wavelet-Based Channel Energy and ImageJ. IEEE J. Sel. Top. Signal Process. 3(1): 81-93 (2009) - [j34]Hsieh-Wei Lee, Bin-Da Liu, King-Chu Hung, Sheau-Fang Lei, Chin-Feng Tsai, Po-Chin Wang, Tsung-Lung Yang, Juen-Sean Lu:
Breast Tumor Classification of Ultrasound Images Using a Reversible Round-Off Nonrecursive 1-D Discrete Periodic Wavelet Transform. IEEE Trans. Biomed. Eng. 56(3): 880-884 (2009) - [j33]Jianwei Zhang, Ming-Yan Yu, Bin-Da Liu, Xiao-Feng Huang:
A High-Speed and EDP-Efficient Range-Matching Scheme for Packet Classification. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 729-733 (2009) - [j32]Yi-Chih Chao, Shih-Tse Wei, Bin-Da Liu, Jar-Ferr Yang:
Combined CAVLC Decoder, Inverse Quantizer, and Transform Kernel in Compact H.264/AVC Decoder. IEEE Trans. Circuits Syst. Video Technol. 19(1): 53-62 (2009) - [c43]Shih-Tse Wei, Shang-Ru Shen, Bin-Da Liu, Jar-Ferr Yang:
Lossless image and video coding based on H.264/AVC intra predictions with simplified interpolations. ICIP 2009: 633-636 - [c42]Chia-Wei Tien, Heng-Yao Lin, Bin-Da Liu, Jar-Ferr Yang:
Transform-domain Partial Prediction Algorithm for Intra Prediction in H.264/AVC. ISCAS 2009: 1245-1248 - [c41]Jianwei Zhang, Yizheng Ye, Bin-Da Liu, Feng Guan:
Self-timed Charge Recycling Search-line Drivers in Content-addressable Memories. ISCAS 2009: 3070-3073 - [c40]Kai-Chi Chang, Kai-Hui Chen, Tsorng-Juu Liang, Bin-Da Liu:
Design of One-cycle Control Power Factor Correction IC with Unipolar Supply Voltage. ISCAS 2009: 3078-3081 - 2008
- [j31]Hsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu:
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 461-468 (2008) - [j30]Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Chien-Hung Tsai, Bin-Da Liu, Soon-Jyh Chang:
A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter. IEICE Trans. Electron. 91-C(5): 809-812 (2008) - [j29]Hsin-Hung Ou, Bin-Da Liu, Soon-Jyh Chang:
A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture. IEICE Trans. Electron. 91-C(9): 1480-1487 (2008) - [j28]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
A Histogram-Based Testing Method for Estimating A/D Converter Performance. IEEE Trans. Instrum. Meas. 57(2): 420-427 (2008) - [j27]Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang:
A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder. IEEE Trans. Multim. 10(1): 31-42 (2008) - [j26]K. Bharanitharan, Bin-Da Liu, Jar-Ferr Yang, Wen-Chih Tsai:
A Low Complexity Detection of Discrete Cross Differences for Fast H.264/AVC Intra Prediction. IEEE Trans. Multim. 10(7): 1250-1260 (2008) - [j25]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 677-682 (2008) - [c39]Heng-Yao Lin, Kuan-Hsien Wu, Bin-Da Liu, Jar-Ferr Yang:
Transformed-based mode decision algorithm for H.264/AVC intraprediction. APCCAS 2008: 1344-1347 - [c38]Hung-Da Hsu, Tsorng-Juu Liang, Bin-Da Liu, Kai-Hui Chen:
Design of a green mode PWM control IC. APCCAS 2008: 1876-1879 - [c37]Yi-Chih Chao, Kuan-Hung Lin, Bin-Da Liu, Jar-Ferr Yang:
An approximate square criterion for H.264/AVC intra mode decision. ICME 2008: 333-336 - [c36]Chih-Hung Kuo, Li-Chuan Chang, Zheng-Wei Liu, Bin-Da Liu:
System level design of a spatio-temporal video resampling architecture. ISCAS 2008: 2797-2800 - 2007
- [j24]Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang:
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electron. Test. 23(6): 549-558 (2007) - [c35]Yi-Chih Chao, Hui-Hsien Tsai, Yu-Hsiu Lin, Jar-Ferr Yang, Bin-Da Liu:
A Novel Design for Computation of All Transforms in H.264/AVC Decoders. ICME 2007: 1914-1917 - [c34]Li-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu:
A Real Time and Low Cost Hardware Architecture for Video Abstraction System. ISCAS 2007: 773-776 - [c33]Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu:
Combined Decoding and Flexible Transform Designs for Effective H.264/AVC Decoders. ISCAS 2007: 3135-3138 - 2006
- [c32]Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, Soon-Jyh Chang:
An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders. APCCAS 2006: 255-258 - [c31]Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu:
Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding. APCCAS 2006: 259-262 - [c30]Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu:
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. APCCAS 2006: 426-429 - [c29]Yi-Chih Chao, Ji-Kun Lin, Jar-Ferr Yang, Bin-Da Liu:
A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter. APCCAS 2006: 1260-1263 - [c28]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories. APCCAS 2006: 1293-1296 - [c27]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
Histogram Based Testing Strategy for ADC. ATS 2006: 51-54 - [c26]Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang:
Low power design of H.264 CAVLC decoder. ISCAS 2006 - [c25]Heng-Yao Lin, Jwu-Jin Yang, Bin-Da Liu, Jar-Ferr Yang:
Efficient deblocking filter architecture for H.264 video coders. ISCAS 2006 - [c24]Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs. ISLPED 2006: 135-138 - 2005
- [j23]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(9): 1819-1831 (2005) - [j22]Chung-Bin Wu, Chin-Yuan Yao, Bin-Da Liu, Jar-Ferr Yang:
DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation. IEEE Trans. Circuits Syst. Video Technol. 15(5): 694-703 (2005) - [j21]Kuo-Huang Lin, Bin-Da Liu:
A gray system modeling approach to the prediction of calibration intervals. IEEE Trans. Instrum. Meas. 54(1): 297-304 (2005) - [c23]Heng-Yao Lin, Yi-Chih Chao, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Combined 2-D transform and quantization architectures for H.264 video coders. ISCAS (2) 2005: 1802-1805 - [c22]Hsin-Hung Ou, Bin-Da Liu:
A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques. ISCAS (3) 2005: 1972-1975 - 2004
- [j20]Wen-Bin Lin, Bin-Da Liu:
Coefficients Generation for the 4th-Order Leapfrog Sigma-Delta A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 87-A(1): 231-242 (2004) - [j19]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(10): 2017-2030 (2004) - [j18]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang, Jiun-Lung Wang:
Efficient recursive structures for forward and inverse discrete cosine transform. IEEE Trans. Signal Process. 52(9): 2665-2669 (2004) - [c21]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. Asian Test Symposium 2004: 52-57 - [c20]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Condensed recursive structures for computing multi-dimensional DCT with arbitrary length. ISCAS (3) 2004: 405-408 - [c19]Zhan-Yuan Cheng, Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Unified selectable fixed-coefficient recursive structures for computing DCT, IMDCT and subband synthesis filtering. ISCAS (3) 2004: 557-560 - [c18]Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu:
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. ISLPED 2004: 252-256 - 2003
- [j17]Chi-Sheng Lin, Bin-Da Liu:
A new successive approximation architecture for low-power low-cost CMOS A/D converter. IEEE J. Solid State Circuits 38(1): 54-62 (2003) - [j16]Chi-Sheng Lin, Jui-Chuan Chang, Bin-Da Liu:
A low-power precomputation-based fully parallel content-addressable memory. IEEE J. Solid State Circuits 38(4): 654-662 (2003) - [j15]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Recursive architectures for realizing modified discrete cosine transform and its inverse. IEEE Trans. Circuits Syst. II Express Briefs 50(1): 38-45 (2003) - [j14]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
Adaptive postprocessors with DCT-based block classifications. IEEE Trans. Circuits Syst. Video Technol. 13(5): 365-375 (2003) - [j13]Chuen-Yau Chen, Yuan-Ta Hsieh, Bin-Da Liu:
Circuit implementation of linguistic-hedge fuzzy logic controller in current-mode approach. IEEE Trans. Fuzzy Syst. 11(5): 624-646 (2003) - [j12]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
A fuzzy-based impulse noise detection and cancellation for real-time processing in video receivers. IEEE Trans. Instrum. Meas. 52(3): 780-784 (2003) - [c17]Che-Hong Chen, Bin-Da Liu, Jar-Ferr Yang:
Direct recursive structures for computing radix-r two-dimensional DCT. ISCAS (4) 2003: 269-272 - [c16]Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu:
Low-power and low-voltage fully parallel content-addressable memory. ISCAS (5) 2003: 373-376 - 2002
- [c15]Wen-Bin Lin, Bin-Da Liu:
The high-resolution multi-tone signal generators. APCCAS (1) 2002: 245-250 - [c14]Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu:
A scalable sorting architecture based on maskable WTA/MAX circuit. ISCAS (4) 2002: 209-212 - [c13]Chi-Sheng Lin, Bin-Da Liu:
Design of a pipelined and expandable sorting architecture with simple control scheme. ISCAS (4) 2002: 217-220 - 2001
- [j11]Bin-Da Liu, Chuen-Yau Chen, Ju-Ying Tsao:
Design of adaptive fuzzy logic controller based on linguistic-hedge concepts and genetic algorithms. IEEE Trans. Syst. Man Cybern. Part B 31(1): 32-53 (2001) - [c12]Chien-Cheng Yu, Weiping Wang, Bin-Da Liu:
A new level converter for low-power applications. ISCAS (1) 2001: 113-116 - [c11]Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang:
Adaptive postprocessors with DCT-based block classifications. ISCAS (5) 2001: 271-274 - [c10]Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu:
A hardware design approach for merge-sorting network. ISCAS (4) 2001: 534-537
1990 – 1999
- 1998
- [j10]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
A graph representation for programmable logic arrays to facilitate testing and logic design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1030-1043 (1998) - 1997
- [j9]Jar-Shone Ker, Chao-Chih Hsu, Yau-Hwang Kuo, Bin-Da Liu:
A fuzzy CMAC model for color reproduction. Fuzzy Sets Syst. 91(1): 53-68 (1997) - [j8]Shih-Chang Hsia, Jar-Ferr Yang, Bin-Da Liu:
Efficient postprocessor for blocky effect removal based on transform characteristics. IEEE Trans. Circuits Syst. Video Technol. 7(6): 924-929 (1997) - [j7]Jar-Shone Ker, Yau-Hwang Kuo, Rong-Chang Wen, Bin-Da Liu:
Hardware implementation of CMAC neural network with reduced storage requirement. IEEE Trans. Neural Networks 8(6): 1545-1556 (1997) - [j6]Bin-Da Liu, Chun-Yueh Huang:
Design and implementation of the tree-based fuzzy logic controller. IEEE Trans. Syst. Man Cybern. Part B 27(3): 475-487 (1997) - 1996
- [j5]Shih-Chang Hsia, Bin-Da Liu, Jar-Ferr Yang, Chien-Hsiu Huang:
A parallel video converter for displaying 4: 3 images on 16: 9 HDTV receivers. IEEE Trans. Circuits Syst. Video Technol. 6(6): 695-699 (1996) - [c9]Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu:
Design of a color reproduction neural network chip with on-chip learning capability. ICIP (2) 1996: 1023-1026 - 1995
- [j4]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang:
Performance-directed compaction for VLSI symbolic layouts. Comput. Aided Des. 27(1): 65-74 (1995) - [j3]Shih-Chang Hsia, Bin-Da Liu, Jar-Ferr Yang, Bor-Long Bai:
VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor. IEEE Trans. Circuits Syst. Video Technol. 5(5): 396-406 (1995) - [j2]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
A practical current sensing technique for IDDQ testing. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 302-310 (1995) - [c8]Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
Built-in intermediate voltage testing for CMOS circuits. ED&TC 1995: 372-377 - [c7]Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu:
Hardware realization of higher-order CMAC model for color calibration. ICNN 1995: 1656-1661 - [c6]Jing-Jou Tang, Bin-Da Liu, Kuen-Jong Lee:
An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs). ISCAS 1995: 393-396 - 1994
- [j1]Kai-Cheng Wei, Bin-Da Liu:
Combining the Folding and Testing for Programmable Logic Arrays. J. Circuits Syst. Comput. 4(3): 305-318 (1994) - [c5]Bin-Da Liu, Chun-Yueh Huang:
Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS Circuits. ISCAS 1994: 537-540 - 1993
- [c4]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Ting-Chung Chang:
A graph-based simplex algorithm for minimizing the layout size and the delay on timing critical paths. ICCAD 1993: 703-708 - [c3]Jar-Shone Ker, Yau-Hwang Kuo, Bin-Da Liu:
Functional Text Pattern Generation for Asynchronous Circuits. ISCAS 1993: 1519-1522 - [c2]Lih-Yang Wang, Yen-Tai Lai, Bin-Da Liu, Tin-Chung Chang:
Layout Compaction with Minimzed Delay Bound on Timing Critical Paths. ISCAS 1993: 1849-1852 - 1992
- [c1]Pao-Chuan Chen, Bin-Da Liu, Jhing-Fa Wang:
Overall consideration of scan design and test generation. ICCAD 1992: 9-12
Coauthor Index
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last updated on 2024-05-29 20:41 CEST by the dblp team
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