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ORCIDMitsuo Ikeda
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2010 – 2019
- 2018
[j9]Takayuki Onishi
, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1930-1938 (2018)- [c13]Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
An HEVC real-time encoding system with high quality HDR color representations. ICCE 2018: 1-2 - 2015
- [c12]Mitsuo Ikeda:
H.265/HEVC encoder for UHDTV. ASP-DAC 2015: 687-688 - [c11]Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu:
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium 2015: 1-24 - [c10]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC 2015: 54- - 2013
- [c9]Jia Su, Koyo Nitta, Mitsuo Ikeda, Atsushi Shimizu:
Residue role assignment based transform partition predetermination on HEVC. ICIP 2013: 2019-2023 - 2012
- [j8]Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma:
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. 95-C(4): 432-440 (2012) - [c8]Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa:
MVC real-time video encoder for full-HDTV 3D video. ICCE 2012: 166-167
2000 – 2009
- 2008
- [c7]Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma:
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. ISCAS 2008: 800-803 - 2007
- [j7]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1055-1059 (2007) - 2006
- [j6]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
Highly accurate de-jittering scheme for broadcast quality video transmission. Syst. Comput. Jpn. 37(10): 81-88 (2006) - 2005
- [j5]Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima:
New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI. IEEE Trans. Consumer Electron. 51(2): 640-641 (2005) - 2004
- [c6]Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima:
A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level. ISCAS (2) 2004: 261-264 - 2003
- [c5]Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo:
A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems. CICC 2003: 177-180 - [c4]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007 - 2000
- [c3]Ken Nakamura, Mitsuo Ikeda, Takeshi Yoshitome, Takeshi Ogura:
Global Rate Control Scheme for MPEG-2 HDTV Parallel Encoding System. ITCC 2000: 195-200
1990 – 1999
- 1999
- [j4]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai:
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19(4): 56-65 (1999) - [j3]Tsuneo Okubo, Mitsuo Ikeda, Yutaka Tashiro, Toshio Kondo, Ryota Kasai, Hiroshi Kotera, Tetsuma Sakurai:
Concurrent and collaborative methodologies in short TAT LSI design and manufacturing. Syst. Comput. Jpn. 30(7): 79-91 (1999) - [j2]Takeshi Yoshitome, Toshihiro Minami, Mitsuo Ikeda, Koyo Nitta, Kazuhito Suguri:
A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI. IEEE Trans. Consumer Electron. 45(4): 1130-1133 (1999) - [c2]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE 1999: 44- - 1996
- [j1]Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato:
Two-chip MPEG-2 video encoder. IEEE Micro 16(2): 51-58 (1996) - [c1]Mitsuo Ikeda, Tsuneo Okubo, Tetsuya Abe, Yoshinori Ito, Yutaka Tashiro, Ryota Kasai:
A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set. ED&TC 1996: 320-327
Coauthor Index
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