Evaluating Beam Sweeping for AoA Estimation with an RIS Prototype: Indoor/Outdoor Field Trials - Dimitris Vordonis; Dimitris Kompostiotis; Vassilis Paliouras; George C. Alexandropoulos; Florin Grec (CoRR, 2025)

A Multiplier-Free RNS-Based CNN Accelerator Exploiting Bit-Level Sparsity - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (IEEE Trans. Emerg. Top. Comput., 2024)

An end-to-end RNS CNN Accelerator - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (6th IEEE International Conference on AI Circuits and Systems, AICAS 2024, Abu Dhabi, United Arab Emirates, April 22-25, 2024, 2024)

SECURED for Health: Scaling Up Privacy to Enable the Integration of the European Health Data Space - Francesco Regazzoni; Gergely Ács; Albert Zoltan Aszalos; Christos Avgerinos; Nikolaos Bakalos; Josep Lluis Berral; Joppe W. Bos; Marco Brohet; Andrés G. Castillo Sanz; Gareth T. Davies; Stefanos Florescu; Pierre-Elisée Flory; et al. (Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024, 2024)

Secrecy Rate Maximization in MIMO RIS-Aided Wireless Communications: A Hardware Accelerator Implementation for Reflection Optimization - Dimitris Kompostiotis; Vassilis Paliouras (IEEE Workshop on Signal Processing Systemsm, SiPS 2024, Cambridge, MA, USA, November 4-6, 2024, 2024)

Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios - Thodoris Spanos; Fran Fabra; José A. Lopez-Salcedo; Gonzalo Seco-Granados; Nikos Kanistras; Ivan Lapin; Vassilis Paliouras (Proceedings of Work-in-Progress in Hardware and Software for Location Computation (WIPHAL 2024), Antwerp, Belgium, June 25-27, 2024, 2024)

Evaluation of RIS-Enabled B5G/6G Indoor Positioning and Mapping using Ray Tracing Models - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras; George C. Alexandropoulos; Florin Grec (CoRR, 2024)

USRP-Based Single Anchor Positioning: AoA with 5G Uplink Signals, and UWB Ranging - Thodoris Spanos; Fran Fabra; José A. Lopez-Salcedo; Gonzalo Seco-Granados; Nikos Kanistras; Ivan Lapin; Vassilis Paliouras (CoRR, 2024)

Path-Based Delay Variation Models for Parallel-Prefix Adders - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)

Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2023)

Modified Logarithmic Multiplication Approximation for Machine Learning - Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (5th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2023, Hangzhou, China, June 11-13, 2023, 2023)

A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (30th IEEE Symposium on Computer Arithmetic, ARITH 2023, Portland, OR, USA, September 4-6, 2023, 2023)

Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization - Emmanouil Kavvousanos; Vasilis Sakellariou; Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (30th IEEE Symposium on Computer Arithmetic, ARITH 2023, Portland, OR, USA, September 4-6, 2023, 2023)

Received Power Maximization with Practical Phase-Dependent Amplitude Response in RIS-Aided OFDM Wireless Communications - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras (IEEE International Conference on Acoustics, Speech and Signal Processing ICASSP 2023, Rhodes Island, Greece, June 4-10, 2023, 2023)

Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case - Dimitris Kompostiotis; Dimitris Vordonis; Vassilis Paliouras; George C. Alexandropoulos (IEEE International Conference on Communications, ICC 2023 - Workshops, Rome, Italy, May 28 - June 1, 2023, 2023)

Invited Paper: Dilithium Hardware-Accelerated Application Using OpenCL-Based High-Level Synthesis - Alexander El-Kady; Apostolos P. Fournaris; Vassilis Paliouras (IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, 2023)

A Regularization Approach to Maximize Common Sub-Expressions in Neural Network Weights - Emmanouil Kavvousanos; Ioannis Kouretas; Vassilis Paliouras; Thanos Stouraitis (30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, 2023)

Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, 2022)

A High-performance RNS LSTM block - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, 2022)

A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation - Emmanouil Kavvousanos; Vassilis Paliouras (11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022, Bremen, Germany, June 8-10, 2022, 2022)

Hardware Aspects of Iterative Receivers for V2X Applications - Thodoris Spanos; Vassilis Paliouras (11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022, Bremen, Germany, June 8-10, 2022, 2022)

Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods - Dimitris Vordonis; Dimitris Kompostiotis; Vassilis Paliouras (11th International Conference on Modern Circuits and Systems Technologies, MOCAST 2022, Bremen, Germany, June 8-10, 2022, 2022)

High-Level Synthesis design approach for Number-Theoretic Multiplier - Alexander El-Kady; Apostolos P. Fournaris; Evangelos Haleplidis; Vassilis Paliouras (30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, 2022)

Hardware Implementation and Performance Analysis of Improved Sphere Decoder in Spatially Correlated Massive MIMO Channels - Dimitris Vordonis; Vassilis Paliouras (IEEE Open J. Commun. Soc., 2021)

Sum Propagate Adders - Giorgos Dimitrakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Emerg. Top. Comput., 2021)

A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees - Ahmed Mahdi; Nikos Kanistras; Vassilis Paliouras (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Sum Propagate Adders - Giorgos Dimitrakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (28th IEEE Symposium on Computer Arithmetic, ARITH 2021, Lyngby, Denmark, June 14-16, 2021, 2021)

Optimizing Deep Learning Decoders for FPGA Implementation - Emmanouil Kavvousanos; Vassilis Paliouras (31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, 2021)

A 5G-code based iterative Non-Binary LDPC decoder - Dimitris Chytas; Vassilis Paliouras (28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, 2021)

On Reducing the Number of Multiplications in RNS-based CNN Accelerators - Vasilis Sakellariou; Vassilis Paliouras; Ioannis Kouretas; Hani H. Saleh; Thanos Stouraitis (28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021, Dubai, United Arab Emirates, November 28 - Dec. 1, 2021, 2021)

A Novel Stochastic Polar Architecture for All-Digital Transmission - Chris Andriakopoulos; Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, 2021)

Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference - Ioannis Kouretas; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, 2021)

An FPGA Accelerator for Spiking Neural Network Simulation and Training - Vasilis Sakellariou; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, 2021)

Hardware Aspects of Parallel Neural Network Implementation - Ioannis Kouretas; Vassilis Paliouras (10th International Conference on Modern Circuits and Systems Technologies, MOCAST 2021, Thessaloniki, Greece, July 5-7, 2021, 2021)

High-Level Synthesis design approach for Number-Theoretic Transform Implementations - Alexander El-Kady; Apostolos P. Fournaris; Thanasis Tsakoulis; Evangelos Haleplidis; Vassilis Paliouras (29th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, Singapore, October 4-7, 2021, 2021)

Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation - Mark G. Arnold; Vassilis Paliouras; Ioannis Kouretas (IEEE Trans. Computers, 2020)

Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations - Kleanthis Papachatzopoulos; Vassilis Paliouras (27th IEEE Symposium on Computer Arithmetic, ARITH 2020, Portland, OR, USA, June 7-10, 2020, 2020)

An Iterative Approach to Syndrome-based Deep Learning Decoding - Emmanouil Kavvousanos; Vassilis Paliouras (IEEE Globecom Workshops, GLOBECOM Workshops 2020, Virtual Event, Taiwan, December 7-11, 2020, 2020)

Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders - Dimitris Chytas; Vassilis Paliouras (27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, 2020)

Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering - Kleanthis Papachatzopoulos; Chris Andriakopoulos; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, 2020)

Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Under- and Overflow Detection in the Residue Logarithmic Number System - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras; John R. Cowles (26th IEEE Symposium on Computer Arithmetic, ARITH 2019, Kyoto, Japan, June 10-12, 2019, 2019)

Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation - Konstantina Karagianni; Vassilis Paliouras (26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, 2019)

Simplified Hardware Implementation of the Softmax Activation Function - Ioannis Kouretas; Vassilis Paliouras (8th International Conference on Modern Circuits and Systems Technologies, MOCAST 2019, Thessaloniki, Greece, May 13-15, 2019, 2019)

Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes - Emmanouil Kavvousanos; Vassilis Paliouras (2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019, 2019)

Sphere Decoder for Massive MIMO Systems - Dimitris Vordonis; Vassilis Paliouras (2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019, 2019)

One-Hot Residue Logarithmic Number Systems - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras; Austin Morgan (29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, Rhodes, Greece, July 1-3, 2019, 2019)

Radix-3 low-complexity modulo-M multipliers - Ioannis Kouretas; Vassilis Paliouras (29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, Rhodes, Greece, July 1-3, 2019, 2019)

Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability - Kleanthis Papachatzopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Reconfigurable RO-Path Delay Sensor - Panagiotis Sakellariou; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Hardware aspects of Long Short Term Memory - Ioannis Kouretas; Vassilis Paliouras (25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, 2018)

Simplified Deep-Learning-based decoders for linear block codes - Emmanouil Kavvousanos; Vassilis Paliouras; Ioannis Kouretas (25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018, 2018)

Data representation and hardware aspects in a fully-folded successive-cancellation polar decoder - Christos Andriakopoulos; Vassilis Paliouras (7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, 2018)

A novel algorithm and hardware architecture for low-complexity soft demappers - Andreas Kalampoukas; Vassilis Paliouras (7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, 2018)

Logarithmic number system for deep learning - Ioannis Kouretas; Vassilis Paliouras (7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, 2018)

Low-cost soft-error compensation for transposed FIR digital filters - Vassilis Paliouras; Konstantina Karagianni; Yann Oster (7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, 2018)

Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines - Vassilis Paliouras; Konstantina Karagianni; Yann Oster (28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018, 2018)

Work in progress: An introduction to computing course using a Python-based experiential approach - Nikolaos M. Avouris; Kyriakos N. Sgarbas; Vassilis Paliouras; Michalis Koukias (2017 IEEE Global Engineering Education Conference, EDUCON 2017, Athens, Greece, April 25-28, 2017, 2017)

An approximate hardware check node for \(λ\)-min-based LDPC decoders - Georgios Perris-Samios; Vassilis Paliouras (25th European Signal Processing Conference, EUSIPCO 2017, Kos, Greece, August 28 - September 2, 2017, 2017)

Logarithmic number system addition-subtraction using fractional normalization - Giorgos Tsiaras; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, 2017)

Hardware trade-offs for massive MIMO uplink detection based on Newton iteration method - Alexios Thanos; Vassilis Paliouras (6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017, Thessaloniki, Greece, May 4-6, 2017, 2017)

Multi-operand logarithmic addition/subtraction based on Fractional Normalization - Giorgos Tsiaras; Vassilis Paliouras (6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017, Thessaloniki, Greece, May 4-6, 2017, 2017)

Application-Specific Low-Power Multipliers - Panagiotis Sakellariou; Vassilis Paliouras (IEEE Trans. Computers, 2016)

Dynamic delay variation behaviour of RNS multiply-add architectures - Kleanthis Papachatzopoulos; Ioannis Kouretas; Vassilis Paliouras (IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, 2016)

Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation - Ioannis Tsatsaragkos; Vassilis Paliouras (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

On the Encoding Complexity of Quasi-Cyclic LDPC Codes - Ahmed Mahdi; Vassilis Paliouras (IEEE Trans. Signal Process., 2015)

A Low Complexity-High Throughput QC-LDPC Encoder - Ahmed Mahdi; Vassilis Paliouras (IEEE Trans. Signal Process., 2014)

Effective sum of squares implementation for BPSK soft-decision decoding - P. Mermigkas; Vassilis Paliouras (21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, 2014)

A technique for the identification of trapping sets in LDPC codes - Christos Vasilopoulos; Vassilis Paliouras (21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, 2014)

Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters - Ioannis Kouretas; Charalambos Basetas; Vassilis Paliouras (IEEE Trans. Computers, 2013)

Delay-variation-tolerant FIR filter architectures based on the Residue Number System - Ioannis Kouretas; Vassilis Paliouras (2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, 2013)

A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm - Nikos Kanistras; Vassilis Paliouras (IEEE Workshop on Signal Processing Systems, SiPS 2013, Taipei City, Taiwan, October 16-18, 2013, 2013)

Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs - Ahmed Mahdi; Panagiotis Sakellariou; Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, 2012)

Low-power two's-complement multiplication based on selective activation - Panagiotis Sakellariou; Vassilis Paliouras (19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, 2012)

Residue arithmetic for designing multiply-add units in the presence of non-gaussian variation - Ioannis Kouretas; Vassilis Paliouras (2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, 2012)

Low-Power Delay Sensors on FPGAs - Panagiotis Sakellariou; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers, 2012)

An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems - Panagiotis Sakellariou; Ioannis Tsatsaragkos; Nikos Kanistras; Ahmed Mahdi; Vassilis Paliouras (2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, 2012)

Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders - Ahmed Mahdi; Vassilis Paliouras (2012 IEEE Workshop on Signal Processing Systems, Quebec City, QC, Canada, October 17-19, 2012, 2012)

Error Floor Compensation for LDPC Codes Using Concatenated Schemes - G. Spourlis; Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (2012 IEEE Workshop on Signal Processing Systems, Quebec City, QC, Canada, October 17-19, 2012, 2012)

Propagation of LLR Saturation and Quantization Error in LDPC Min-Sum Iterative Decoding - Nikos Kanistras; Ioannis Tsatsaragkos; Vassilis Paliouras (2012 IEEE Workshop on Signal Processing Systems, Quebec City, QC, Canada, October 17-19, 2012, 2012)

Impact of Approximation Error on the Decisions of LDPC Decoding - Nikos Kanistras; Vassilis Paliouras (J. Signal Process. Syst., 2011)

Towards a Quaternion Complex Logarithmic Number System - Mark G. Arnold; John R. Cowles; Vassilis Paliouras; Ioannis Kouretas (20th IEEE Symposium on Computer Arithmetic, ARITH 2011, Tübingen, Germany, 25-27 July 2011, 2011)

A Residue Logarithmic Number System ALU using interpolation and cotransformation - Mark G. Arnold; Ioannis Kouretas; Vassilis Paliouras (22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011, 2011)

A flexible high-throughput hardware architecture for a gaussian noise generator - Ioannis Paraskevakos; Vassilis Paliouras (Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2011, May 22-27, 2011, Prague Congress Center, Prague, Czech Republic, 2011)

A syndrome-based LDPC decoder with very low error floor - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (17th International Conference on Digital Signal Processing, DSP 2011, Corfu, Greece, July 6-8, 2011, 2011)

Multiple LDPC decoder of very low bit-error rate - Ioannis Tsatsaragkos; Nikos Kanistras; Vassilis Paliouras (17th International Conference on Digital Signal Processing, DSP 2011, Corfu, Greece, July 6-8, 2011, 2011)

On the impact of encoding on the complexity of residue arithmetic circuits - E. Theodorakis; Vassilis Paliouras (18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, 2011)

Next generation millimeter wave backhaul radio: Overall system design for GbE 60GHz PtP wireless radio of high CMOS integration - Rodoula Makri; Petros Tsenes; Dimitrios Economou; Yannis Papananos; Dimitrios Dervenis; Michael K. Birbas; John C. Kikidis; Vassilis Paliouras; Grigorios Kalivas; Alexios N. Birbas; Panos Karaivazoglou; Yorgos Stratakos; et al. (18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, 2011)

Digital baseband challenges for a 60GHz gigabit link - Nikos Kanistras; Ioannis Tsatsaragkos; Ahmed Mahdi; Konstantina Karagianni; Vassilis Paliouras; Fotios Gioulekas; E. Lalos; Kostas Adaos; Michael K. Birbas; Panos Karaivazoglou; M. V. Koziotis; M. Perakis (18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, Beirut, Lebanon, December 11-14, 2011, 2011)

A flexible layered LDPC decoder - Ioannis Tsatsaragkos; Vassilis Paliouras (8th International Symposium on Wireless Communication Systems, ISWCS 2011, Aachen, Germany, November 6-9, 2011, 2011)

Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems - Andreas Brokalakis; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon, 2011)

An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes - Ahmed Mahdi; Nikos Kanistras; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2011, October 4-7, 2011, Beirut, Lebanon, 2011)

RNS multi-voltage low-power multiply-add unit - Ioannis Kouretas; Vassilis Paliouras (17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, 2010)

VLSI implementation and performance of turbo decoding stopping criteria - Angelos Spanos; Vassilis Paliouras (17th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Greece, 12-15 December, 2010, 2010)

Residue arithmetic bases for reducing delay variation - Ioannis Kouretas; Vassilis Paliouras (International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, 2010)

Residue Arithmetic for Designing Low-Power Multiply-Add Units - Ioannis Kouretas; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 20th International Workshop, PATMOS 2010, Grenoble, France, September 7-10, 2010, Revised Selected Papers, 2010)

A Low-Complexity High-Radix RNS Multiplier - Ioannis Kouretas; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information - Theodoros Giannopoulos; Vassilis Paliouras (J. Signal Process. Syst., 2009)

Variation-tolerant Design Using Residue Number System - Ioannis Kouretas; Vassilis Paliouras (12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, 2009)

High-radix residue arithmetic bases for low-power DSP systems - Ioannis Kouretas; Vassilis Paliouras (16th International Conference on Digital Signal Processing, DSP 2009, Santorini, Greece, July 5-7, 2009, 2009)

Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units - Ioannis Kouretas; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers, 2009)

Low-power logarithmic number system addition/subtraction and their impact on digital filters - Ioannis Kouretas; Charalambos Basetas; Vassilis Paliouras (International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, 2008)

A frequency-domain interpolation implementation for OFDM transmitters - Eleni Fotopoulou; Vassilis Paliouras; Thanos Stouraitis (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

Relationship among BER, power consumption and PAPR - Theodoros Giannopoulos; Vassilis Paliouras (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

Roundoff error effects on a Quasi-Newton frequency domain channel equalizer - Panos Karaivazoglou; Konstantina Karagianni; Vassilis Paliouras; Kostas Berberidis (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

On the implementation of bus-based architectures for LDPC decoding - G. Aggouras; Vassilis Paliouras (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

Impact of roundoff errors in LDPC decoding - Nikos Kanistras; Vassilis Paliouras (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

Packet detector for multiband UWB - D. Pettas; Vassilis Paliouras (Third International Symposium on Wireless Pervasive Computing, ISWPC 2008, May 7-9, 2008, Santorini, Greece, Proceedings, 2008)

Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication - Ioannis Kouretas; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, 2008)

Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding - Nikos Kanistras; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2008, October 8-10, 2008, Washington, D.C. Metro Area, USA, 2008)

Low-Power Digital Filtering Based on the Logarithmic Number System - Charalambos Basetas; Ioannis Kouretas; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, 2007)

On The Complexity of Joint Demodulation and Convolutional Decoding - Dimitris Gkrimpas; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, 2007)

Editorial - Johan Vounckx; Vassilis Paliouras (J. Low Power Electron., 2006)

Novel efficient weighting factors for PTS-based PAPR reduction in low-power OFDM transmitters - Theodoros Giannopoulos; Vassilis Paliouras (14th European Signal Processing Conference, EUSIPCO 2006, Florence, Italy, September 4-8, 2006, 2006)

A novel technique for low-power D/A conversion based on PAPR reduction - Theodoros Giannopoulos; Vassilis Paliouras (International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006)

Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters - Theodoros Giannopoulos; Vassilis Paliouras (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, 2006)

Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems - Konstantina Karagianni; Vassilis Paliouras; Theodoros Giannopoulos (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, 2006)

Simplified Criteria for Early Iterative Decoding Termination - Spyros Gidaros; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, 2006)

A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information - Theodoros Giannopoulos; Vassilis Paliouras (Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, 2006)

Using CLNS for FFTs in OFDM demodulation of UWB receivers - Panagiotis D. Vouzis; Mark G. Arnold; Vassilis Paliouras (International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, 2005)

Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction - Theodoros Giannopoulos; Vassilis Paliouras (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, 2005)

Low-Power Aspects of Nonlinear Signal Processing - Konstantina Karagianni; Vassilis Paliouras (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, 2005)

Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings - Vassilis Paliouras; Johan Vounckx; Diederik Verkest (Springer, 2005)

A novel architecture and a systematic graph-based optimization methodology for modulo multiplication - Giorgos Dimitrakopoulos; Vassilis Paliouras (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

An efficient computational method and a VLSI architecture for digital filtering of CP-OFDM signals - Eleni Fotopoulou; Vassilis Paliouras (Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November - 3 December 2004, 2004)

An efficient architecture for peak-to-average power ratio reduction in OFDM systems in the presence of pulse-shaping filtering - Theodoros Giannopoulos; Vassilis Paliouras (Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, 2004)

An efficient memory compression scheme for 8 k FFT in a DVB-T receiver and the corresponding error model - Stamatis Krommydas; Vassilis Paliouras (Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, 2004)

Optimal Logarithmic Representation in Terms of SNR Behavior - Panagiotis D. Vouzis; Vassilis Paliouras (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings - Enrico Macii; Odysseas G. Koufopavlou; Vassilis Paliouras (Springer, 2004)

A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems - Eleni Fotopoulou; Vassilis Paliouras; Thanos Stouraitis (Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, 2003)

High-radix redundant circuits for RNS modulo r\(^n\)-1, r\(^n\), or r\(^n\)+1 - Ioannis Kouretas; Vassilis Paliouras (Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, 2003)

Multi-voltage low power convolvers using the polynomial residue number system - Vassilis Paliouras; Alexander Skavantzos; Thanos Stouraitis (Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, 2002)

High-radix modulo r\(^n\) - 1 multipliers and adders - Ioannis Kouretas; Vassilis Paliouras (Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, 2002)

Operation-Saving VLSI Architectures for 3D Geometrical Transformations - Konstantina Karagianni; Vassilis Paliouras; George Diamantakos; Thanos Stouraitis (IEEE Trans. Computers, 2001)

Low-Power Properties of the Logarithmic Number System - Vassilis Paliouras; Thanos Stouraitis (15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, 2001)

VLSI architectures for blind equalization based on fractional-order statistics - Vassilis Paliouras; J. Dagres; Panagiotis Tsakalides; Thanos Stouraitis (Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, 2001)

Signal activity and power consumption reduction using the logarithmic number system - Vassilis Paliouras; Thanos Stouraitis (Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, 2001)

High-radix residue number system forward and inverse converters - Vassilis Paliouras; Thanos Stouraitis (Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, 2000)

Logarithmic Number System for Low-Power Arithmetic - Vassilis Paliouras; Thanos Stouraitis (Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, 2000)

Novel high-radix residue number system multipliers and adders - Vassilis Paliouras; Thanos Stouraitis (Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, 1999)

A very-long instruction word digital signal processor based on the logarithmic number system - Vassilis Paliouras; J. Karagiannis; G. Aggouras; Thanos Stouraitis (5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998, 1998)

A VLSI architecture for fast and accurate floating-point sine/cosine evaluation - Vassilis Paliouras; Konstantina Karagianni; Thanos Stouraitis (5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998, 1998)

Area-time performance of VLSI FIR filter architectures based on residue arithmetic - Vassilis Paliouras; Thanos Stouraitis (23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, 1997)

An operation-saving VLSI geometry engine core - Konstantina Karagianni; George Diamantakos; Vassilis Paliouras; Thanos Stouraitis (1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '97, Munich, Germany, April 21-24, 1997, 1997)

Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function - E. N. Malamas; Vassilis Paliouras; Thanos Stouraitis (Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996, 1996)

A Novel Algorithm for Multi-Operand Logarithmic Number System Addition and Subtraction Using Polynominal Approximation - I. Orginos; Vassilis Paliouras; Thanos Stouraitis (1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, 1995)

Systematic Design of Multi-Modulus/Multi-Function Residue Number System Processors - Vassilis Paliouras; Thanos Stouraitis (1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, 1994)

Systematic design of full adder-based architectures for convolution - Dimitrios Soudris; Vassilis Paliouras; Thanos Stouraitis; Alexander Skavantzos; Constantinos E. Goutis (IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '93, Minneapolis, Minnesota, USA, April 27-30, 1993, 1993)

Methodology for the Design of Signed-digit DSP Processors - Vassilis Paliouras; Dimitrios Soudris; Thanos Stouraitis (1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, 1993)

Systematic development of architectures for multidimensional DSP using the residue number system - Dimitrios Soudris; Vassilis Paliouras; Thanos Stouraitis (1992 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '92, San Francisco, California, USA, March 23-26, 1992, 1992)