Energy-Efficient Design Methodologies: High-Performance VLSI Adders - Bart R. Zeydel; Dursun Baran; Vojin G. Oklobdzija (IEEE J. Solid State Circuits, 2010)

Logic Style Comparison for Ultra Low Power Operation in 65nm Technology - Mandeep Singh; Christophe Giacomotto; Bart R. Zeydel; Vojin G. Oklobdzija (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, 2007)

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS - Steven K. Hsu; Sanu K. Mathew; Mark A. Anders; Bart R. Zeydel; Vojin G. Oklobdzija; Ram K. Krishnamurthy; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2006)

Energy optimization of pipelined digital systems using circuit sizing and supply scaling - Hoang Q. Dao; Bart R. Zeydel; Vojin G. Oklobdzija (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Circuit Design Style for Energy Efficiency: LSDL and Compound Domino - Xiao Yan Yu; Robert K. Montoye; Kevin J. Nowka; Bart R. Zeydel; Vojin G. Oklobdzija (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, 2006)

Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations - Bart R. Zeydel; Vojin G. Oklobdzija (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, 2006)

Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design - Milena Vratonjic; Bart R. Zeydel; Vojin G. Oklobdzija (Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, 2006)

Comparison of high-performance VLSI adders in the energy-delay space - Vojin G. Oklobdzija; Bart R. Zeydel; Hoang Q. Dao; Sanu Mathew; Ram Krishnamurthy (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Efficient Mapping of Addition Recurrence Algorithms in CMOS - Bart R. Zeydel; Theo T. J. H. Kluter; Vojin G. Oklobdzija (17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, 2005)

Architectural Considerations for Energy Efficiency - Hoang Q. Dao; Bart R. Zeydel; Vojin G. Oklobdzija (23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, 2005)

Low- and Ultra Low-Power Arithmetic Units: Design and Comparison - Milena Vratonjic; Bart R. Zeydel; Vojin G. Oklobdzija (23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, 2005)

Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders - Vojin G. Oklobdzija; Bart R. Zeydel; Hoang Q. Dao; Sanu Mathew; Ram Krishnamurthy (16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, 2003)

Energy minimization method for optimal energy-delay extraction - Hoang Q. Dao; Bart R. Zeydel; Vojin G. Oklobdzija (ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, 2003)

Energy Optimization of High-Performance Circuits - Hoang Q. Dao; Bart R. Zeydel; Vojin G. Oklobdzija (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, 2003)