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- affiliation: University of California, San Diego, USA
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2020 – today
- 2025
[i3]Basar Kütükçü, Sinan Xie, Sabur Baidya, Sujit Dey:
JExplore: Design Space Exploration Tool for Nvidia Jetson Boards. CoRR abs/2502.15773 (2025)- 2024
- [j94]Jianrong Chen
, Sujit Dey:
Graph-Based Multi-Modal Multi-View Fusion for Facial Action Unit Recognition. IEEE Access 12: 69310-69324 (2024) - [j93]Jianrong Chen, Sujit Dey, Lei Wang, Ning Bi, Peng Liu:
Attention-Based Multi-Modal Multi-View Fusion Approach for Driver Facial Expression Recognition. IEEE Access 12: 137203-137221 (2024) - [j92]Onur N. Tepencelik, Wenchuan Wei, Pamela C. Cosman, Sujit Dey:
Body and Head Orientation Estimation From Low-Resolution Point Clouds in Surveillance Settings. IEEE Access 12: 141460-141475 (2024) - [j91]Basar Kütükçü, Sabur Baidya, Sujit Dey:
Fast and Scalable Design Space Exploration for Deep Learning on Embedded Systems. IEEE Access 12: 148254-148266 (2024) - [j90]Bryse Flowers, Sujit Dey:
BRIC: Bottom-Up Residual Vector Quantization for Learned Image Compression. IEEE Access 12: 153105-153126 (2024) - [j89]Basar Kütükçü, Sabur Baidya, Sujit Dey:
SLEXNet: Adaptive Inference Using Slimmable Early Exit Neural Networks. ACM Trans. Embed. Comput. Syst. 23(6): 104:1-104:29 (2024) - [j88]Yufan Zhang, Sujit Dey, Yuanyuan Shi:
Optimal Vehicle Charging in Bilevel Power-Traffic Networks via Charging Demand Function. IEEE Trans. Smart Grid 15(3): 3054-3065 (2024) - [j87]Bryse Flowers, Yu-Jen Ku, Sabur Baidya, Sujit Dey:
Utilizing Reinforcement Learning for Adaptive Sensor Data Sharing Over C-V2X Communications. IEEE Trans. Veh. Technol. 73(3): 4051-4066 (2024) - [j86]Samuel Thornton, Sujit Dey:
Multi-Modal Data and Model Reduction for Enabling Edge Fusion in Connected Vehicle Environments. IEEE Trans. Veh. Technol. 73(8): 11979-11994 (2024) - [c158]Sinan Xie, Jared Leitner, Sujit Dey:
Personalized Impact of Lifestyle on Type 1 Diabetes Patients: A Comprehensive Regression Analysis. ICHI 2024: 214-221 - 2023
- [j85]Suhwan Jung, Hyoil Kim, Xinyu Zhang, Sujit Dey:
GaMiCO: Game-slicing based multi-interface computation offloading in 5G vehicular networks. J. Commun. Networks 25(4): 491-506 (2023) - [j84]Jared Leitner, Alexander Behnke, Po-Han Chiang, Michele Ritter, Marlene Millen, Sujit Dey:
Classification of Patient Recovery From COVID-19 Symptoms Using Consumer Wearables and Machine Learning. IEEE J. Biomed. Health Informatics 27(3): 1271-1282 (2023) - [j83]Yu-Jen Ku, Sabur Baidya, Sujit Dey:
Uncertainty-Aware Task Offloading for Multi-Vehicle Perception Fusion Over Vehicular Edge Computing. IEEE Trans. Veh. Technol. 72(11): 14906-14923 (2023) - [c157]Bhanu Garg, Alexander Postlmayr, Pamela C. Cosman, Sujit Dey:
Short: Deep Learning Approach to Skeletal Performance Evaluation of Physical Therapy Exercises. CHASE 2023: 168-172 - [c156]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems. SOCC 2023: 1-6 - [i2]Yufan Zhang, Sujit Dey, Yuanyuan Shi:
Optimal Vehicle Charging in Bilevel Power-Traffic Networks via Charging Demand Function. CoRR abs/2304.11284 (2023) - [i1]Onur N. Tepencelik, Wenchuan Wei, Pamela C. Cosman, Sujit Dey:
Analyzing Head Orientation of Neurotypical and Autistic Individuals in Triadic Conversations. CoRR abs/2311.00343 (2023) - 2022
- [j82]Samuel Thornton, Bryse Flowers, Sujit Dey:
Multi-Source Feature Fusion for Object Detection Association in Connected Vehicle Environments. IEEE Access 10: 131841-131854 (2022) - [j81]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems. ACM Trans. Embed. Comput. Syst. 21(5): 55:1-55:29 (2022) - [j80]Jared Leitner, Po-Han Chiang, Sujit Dey:
Personalized Blood Pressure Estimation Using Photoplethysmography: A Transfer Learning Approach. IEEE J. Biomed. Health Informatics 26(1): 218-228 (2022) - [c155]Jared Leitner, Po-Han Chiang, Brian Khan, Sujit Dey:
An mHealth Lifestyle Intervention Service for Improving Blood Pressure using Machine Learning and IoMTs. ICDH 2022: 142-150 - [c154]Yu-Jen Ku, Bryse Flowers, Samuel Thornton, Sabur Baidya, Sujit Dey:
Adaptive C-V2X Sidelink Communications for Vehicular Applications Beyond Safety Messages. VTC Spring 2022: 1-6 - 2021
- [j79]Xueshi Hou, Sujit Dey, Jianzhong Zhang, Madhukar Budagavi:
Predictive Adaptive Streaming to Enable Mobile 360-Degree and VR Experiences. IEEE Trans. Multim. 23: 716-731 (2021) - [j78]Yu-Jen Ku, Sabur Baidya, Sujit Dey:
Adaptive Computation Partitioning and Offloading in Real-Time Sustainable Vehicular Edge Computing. IEEE Trans. Veh. Technol. 70(12): 13221-13237 (2021) - [c153]Basar Kütükçü, Sabur Baidya, Anand Raghunathan, Sujit Dey:
Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems. AICAS 2021: 1-4 - [c152]Onur N. Tepencelik, Wenchuan Wei, Leanne Chukoskie, Pamela C. Cosman, Sujit Dey:
Body and Head Orientation Estimation with Privacy Preserving LiDAR Sensors. EUSIPCO 2021: 766-770 - [c151]Jianrong Chen, Sujit Dey, Lei Wang, Ning Bi, Peng Liu:
Multi-Modal Fusion Enhanced Model For Driver's Facial Expression Recognition. ICME Workshops 2021: 1-4 - [c150]Bryse Flowers, Xinyu Zhang, Sujit Dey:
Low Overhead Codebook Design for mmWave Roadside Units Placed at Smart Intersections. PIMRC 2021: 366-372 - 2020
- [j77]Wenchuan Wei, Carter McElroy, Sujit Dey:
Using Sensors and Deep Learning to Enable On-Demand Balance Evaluation for Effective Physical Therapy. IEEE Access 8: 99889-99899 (2020) - [j76]Xueshi Hou, Sujit Dey:
Motion Prediction and Pre-Rendering at the Edge to Enable Ultra-Low Latency Mobile 6DoF Experiences. IEEE Open J. Commun. Soc. 1: 1674-1690 (2020) - [j75]Yu-Jen Ku, Po-Han Chiang, Sujit Dey:
Real-Time QoS Optimization for Vehicular Edge Computing With Off-Grid Roadside Units. IEEE Trans. Veh. Technol. 69(10): 11975-11991 (2020) - [c149]Samuel Thornton, Sujit Dey:
Machine Learning Techniques for Vehicle Matching with Non-Overlapping Visual Features. CAVS 2020: 1-6 - [c148]Sabur Baidya, Yu-Jen Ku, Hengyu Zhao, Jishen Zhao, Sujit Dey:
Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications. DAC 2020: 1-6 - [c147]Song Wang, Jingqi Huang, Xinyu Zhang, Hyoil Kim, Sujit Dey:
X-Array: approximating omnidirectional millimeter-wave coverage using an array of phased arrays. MobiCom 2020: 5:1-5:14
2010 – 2019
- 2019
- [j74]Po-Han Chiang, Sujit Dey:
Offline and Online Learning Techniques for Personalized Blood Pressure Prediction and Health Behavior Recommendations. IEEE Access 7: 130854-130864 (2019) - [j73]Wenchuan Wei, Yao Lu, Eric Rhoden, Sujit Dey:
User performance evaluation and real-time guidance in cloud-based physical therapy monitoring and guidance system. Multim. Tools Appl. 78(7): 9051-9081 (2019) - [c146]Xueshi Hou, Jianzhong Zhang, Madhukar Budagavi, Sujit Dey:
Head and Body Motion Prediction to Enable Mobile VR Experiences with Low Latency. GLOBECOM 2019: 1-7 - [c145]Jared Leitner, Po-Han Chiang, Sujit Dey:
Personalized Blood Pressure Estimation using Photoplethysmography and Wavelet Decomposition. HealthCom 2019: 1-6 - [c144]Wenchuan Wei, Sujit Dey:
Center of Mass Estimation for Balance Evaluation Using Convolutional Neural Networks. ICHI 2019: 1-7 - [c143]Yu-Jen Ku, Sujit Dey:
Sustainable Vehicular Edge Computing Using Local and Solar-Powered Roadside Unit Resources. VTC Fall 2019: 1-7 - 2018
- [j72]Po-Han Chiang, Ranjini Guruprasad, Sujit Dey:
Optimal Use of Harvested Solar, Hybrid Storage and Base Station Resources for Green Cellular Networks. IEEE Trans. Green Commun. Netw. 2(3): 707-720 (2018) - [j71]Xueshi Hou, Yao Lu, Sujit Dey:
Novel Hybrid-Cast Approach to Reduce Bandwidth and Latency for Cloud-Based Virtual Space. ACM Trans. Multim. Comput. Commun. Appl. 14(3s): 58:1-58:25 (2018) - [c142]Po-Han Chiang, Sujit Dey:
Personalized Effect of Health Behavior on Blood Pressure: Machine Learning Based Prediction and Recommendation. HealthCom 2018: 1-6 - [c141]Yu-Jen Ku, Po-Han Chiang, Sujit Dey:
Quality of Service Optimization for Vehicular Edge Computing with Solar-Powered Road Side Units. ICCCN 2018: 1-10 - [c140]Wenchuan Wei, Carter McElroy, Sujit Dey:
Human Action Understanding and Movement Error Identification for the Treatment of Patients with Parkinson's Disease. ICHI 2018: 180-190 - [c139]Xueshi Hou, Sujit Dey, Jianzhong Zhang, Madhukar Budagavi:
Predictive View Generation to Enable Mobile 360-degree and VR Experiences. VR/AR Network@SIGCOMM 2018: 20-26 - 2017
- [j70]Yao Lu, Yao Liu, Sujit Dey:
Asymmetric and selective object rendering for optimized Cloud Mobile 3D Display Gaming user experience. Multim. Tools Appl. 76(18): 18291-18320 (2017) - [j69]Ranjini Guruprasad, Sujit Dey:
User QoS-Aware Adaptive RF Chain Switching for Power Efficient Cooperative Base Stations. IEEE Trans. Green Commun. Netw. 1(4): 409-422 (2017) - [c138]Xueshi Hou, Yao Lu, Sujit Dey:
Wireless VR/AR with Edge/Cloud Computing. ICCCN 2017: 1-8 - [c137]Weiheng Ni, Po-Han Chiang, Sujit Dey:
Energy Efficient Hybrid Beamforming in Massive MU-MIMO Systems via Eigenmode Selection. iThings/GreenCom/CPSCom/SmartData 2017: 400-406 - 2016
- [j68]Chetan Kumar Verma, Michael Hart, Sandeep Bhatkar, Aleatha Parker-Wood, Sujit Dey:
Improving Scalability of Personalized Recommendation Systems for Enterprise Knowledge Workers. IEEE Access 4: 204-215 (2016) - [j67]Yao Lu, Sujit Dey:
JAVRE: A Joint Asymmetric Video Rendering and Encoding Approach to Enable Optimized Cloud Mobile 3D Virtual Immersive User Experience. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(4): 544-559 (2016) - [j66]Kyuho Son, Ranjini Guruprasad, Santosh V. Nagaraj, Mahasweta Sarkar, Sujit Dey:
Dynamic cell reconfiguration framework for energy conservation in cellular wireless networks. J. Commun. Networks 18(4): 567-579 (2016) - [j65]Hasti A. Pedersen, Sujit Dey:
Enhancing Mobile Video Capacity and Quality Using Rate Adaptation, RAN Caching and Processing. IEEE/ACM Trans. Netw. 24(2): 996-1010 (2016) - [j64]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
Emulation-Based Analysis of System-on-Chip Performance Under Variations. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3401-3414 (2016) - [c136]Xueshi Hou, Yao Lu, Sujit Dey:
A Novel Hyper-Cast Approach to Enable Cloud-Based Virtual Classroom Applications. ISM 2016: 533-536 - 2015
- [j63]Chetan Kumar Verma, Sujit Dey:
Methods to Obtain Training Videos for Fully Automated Application-Specific Classification. IEEE Access 3: 1188-1205 (2015) - [j62]Chetan Kumar Verma, Vijay Mahadevan, Nikhil Rasiwasia, Gaurav Aggarwal, Ravi Kant, Alejandro Jaimes, Sujit Dey:
Construction and evaluation of ontological tag trees. Expert Syst. Appl. 42(24): 9587-9602 (2015) - [j61]Yao Lu, Yao Liu, Sujit Dey:
Cloud Mobile 3D Display Gaming User Experience Modeling and Optimization by Asymmetric Graphics Rendering. IEEE J. Sel. Top. Signal Process. 9(3): 517-532 (2015) - [j60]Yao Liu, Sujit Dey, Fatih Ulupinar, Michael Luby, Yinian Mao:
Deriving and Validating User Experience Model for DASH Video Streaming. IEEE Trans. Broadcast. 61(4): 651-665 (2015) - [j59]Yao Liu, Sujit Dey, Yao Lu:
Enhancing Video Encoding for Cloud Gaming Using Rendering Information. IEEE Trans. Circuits Syst. Video Technol. 25(12): 1960-1974 (2015) - [j58]Ranjini Guruprasad, Sujit Dey:
Battery Aware Video Delivery Techniques Using Rate Adaptation and Base Station Reconfiguration. IEEE Trans. Multim. 17(9): 1630-1645 (2015) - [j57]Ali Mirtar, Sujit Dey, Anand Raghunathan:
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding. ACM Trans. Design Autom. Electr. Syst. 20(4): 50:1-50:27 (2015) - [j56]Ali Mirtar, Sujit Dey, Anand Raghunathan:
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1017-1030 (2015) - [c135]Dennis Shen, Yao Lu, Sujit Dey:
Motion data alignment for real-time guidance in avatar based physical therapy training system. HealthCom 2015: 238-244 - [c134]Ranjini Guruprasad, Kyuho Son, Sujit Dey:
Power-efficient base station operation through user QoS-aware adaptive RF chain switching technique. ICC 2015: 244-250 - [c133]Yao Lu, Yao Liu, Sujit Dey:
Optimizing Cloud Mobile 3D Display Gaming user experience by asymmetric object of interest rendering. ICC 2015: 6842-6848 - [c132]Chetan Kumar Verma, Michael Hart, Sandeep Bhatkar, Aleatha Parker-Wood, Sujit Dey:
Access Prediction for Knowledge Workers in Enterprise Data Repositories. ICEIS (1) 2015: 150-161 - [c131]Yao Liu, Yao Liu, Sujit Dey:
A Joint Asymmetric Graphics Rendering and Video Encoding Approach for Optimizing Cloud Mobile 3D Display Gaming User Experience. ISM 2015: 421-428 - [c130]Po-Han Chiang, Ranjini Guruprasad, Sujit Dey:
Renewable energy-aware video download in cellular networks. PIMRC 2015: 1622-1627 - [c129]Wenchuan Wei, Yao Lu, Catherine D. Printz, Sujit Dey:
Motion data alignment and real-time guidance in cloud-based virtual training system. Wireless Health 2015: 13:1-13:8 - 2014
- [j55]Yao Liu, Shaoxuan Wang, Sujit Dey:
Content-Aware Modeling and Enhancing User Experience in Cloud Mobile Rendering and Streaming. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(1): 43-56 (2014) - [j54]Hasti Ahlehagh, Sujit Dey:
Video-Aware Scheduling and Caching in the Radio Access Network. IEEE/ACM Trans. Netw. 22(5): 1444-1462 (2014) - [c128]Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan:
Variation Aware Cache Partitioning for Multithreaded Programs. DAC 2014: 199:1-199:6 - [c127]Yao Lu, Yao Liu, Sujit Dey:
Enhancing Cloud Mobile 3D display gaming user experience by asymmetric graphics rendering. ICNC 2014: 368-374 - [c126]Vivek Joy Kozhikkottu, Swagath Venkataramani, Sujit Dey, Anand Raghunathan:
Variation tolerant design of a vector processor for recognition, mining and synthesis. ISLPED 2014: 239-244 - [c125]Hasti A. Pedersen, Sujit Dey:
Mobile device video caching to improve video qoe and cellular network capacity. MSWiM 2014: 103-107 - [c124]Chetan Kumar Verma, Vijay Mahadevan, Nikhil Rasiwasia, Gaurav Aggarwal, Ravi Kant, Alejandro Jaimes, Sujit Dey:
Construction of tag ontological graphs by locally minimizing weighted average hops. WWW (Companion Volume) 2014: 393-394 - 2013
- [j53]Shaoxuan Wang, Sujit Dey:
Adaptive Mobile Cloud Computing to Enable Rich Mobile Multimedia Applications. IEEE Trans. Multim. 15(4): 870-883 (2013) - [c123]Yao Liu, Sujit Dey, Don Gillies, Fatih Ulupinar, Michael Luby:
User Experience Modeling for DASH Video. PV 2013: 1-8 - [c122]Ranjini Guruprasad, Sujit Dey:
Rate adaptation and base station reconfiguration for battery efficient video download. WCNC 2013: 339-344 - [c121]Hasti Ahlehagh, Sujit Dey:
Adaptive Bit Rate capable video caching and scheduling. WCNC 2013: 1357-1362 - [c120]Kyuho Son, Santosh V. Nagaraj, Mahasweta Sarkar, Sujit Dey:
QoS-aware dynamic cell reconfiguration for energy conservation in cellular networks. WCNC 2013: 2022-2027 - [c119]Chetan Kumar Verma, Sujit Dey:
Fully Automated Learning for Application-Specific Web Video Classification. Web Intelligence 2013: 307-314 - 2012
- [j52]Shaoxuan Wang, Sujit Dey:
Cloud mobile gaming: modeling and measuring user experience in mobile wireless networks. ACM SIGMOBILE Mob. Comput. Commun. Rev. 16(1): 10-21 (2012) - [j51]Saumya Chandra, Anand Raghunathan, Sujit Dey:
Variation-Aware Voltage Level Selection. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 925-936 (2012) - [c118]Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan:
Recovery-based design for variation-tolerant SoCs. DAC 2012: 826-833 - [c117]Ali Mirtar, Sujit Dey, Anand Raghunathan:
Adaptation of video encoding to address dynamic thermal management effects. IGCC 2012: 1-10 - [c116]Shaoxuan Wang, Yao Liu, Sujit Dey:
Wireless network aware cloud scheduler for scalable cloud mobile gaming. ICC 2012: 2081-2086 - [c115]Hasti Ahlehagh, Sujit Dey:
Hierarchical video caching in wireless cloud: Approaches and algorithms. ICC 2012: 7082-7087 - [c114]Yao Liu, Shaoxuan Wang, Sujit Dey:
Modeling, characterizing, and enhancing user experience in Cloud Mobile Rendering. ICNC 2012: 739-745 - [c113]Sujit Dey:
Cloud Mobile Media: Opportunities, challenges, and directions. ICNC 2012: 929-933 - [c112]Hasti Ahlehagh, Sujit Dey:
Video caching in Radio Access Network: Impact on delay and capacity. WCNC 2012: 2276-2281 - 2011
- [c111]Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey:
VESPA: Variability emulation for System-on-Chip performance analysis. DATE 2011: 2-7 - 2010
- [j50]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Aware System-Level Power Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1173-1184 (2010) - [c110]Shaoxuan Wang, Sujit Dey:
Rendering Adaptation to Address Communication and Computation Constraints in Cloud Mobile Gaming. GLOBECOM 2010: 1-6 - [c109]Shaoxuan Wang, Sujit Dey:
Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming. WCNC 2010: 1-6
2000 – 2009
- 2009
- [j49]Shoubhik Mukhopadhyay, Curt Schurgers, Sujit Dey:
Enabling rich mobile applications: joint computation and communication scheduling. ACM SIGMOBILE Mob. Comput. Commun. Rev. 13(3): 14-25 (2009) - [j48]Shoubhik Mukhopadhyay, Curt Schurgers, Debashis Panigrahi, Sujit Dey:
Model-Based Techniques for Data Reliability in Wireless Sensor Networks. IEEE Trans. Mob. Comput. 8(4): 528-543 (2009) - [j47]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Tolerant Dynamic Power Management at the System-Level. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1220-1232 (2009) - [c108]Shaoxuan Wang, Sujit Dey:
Modeling and Characterizing User Experience in a Cloud Server Based Mobile Gaming Approach. GLOBECOM 2009: 1-7 - [c107]Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy:
Coping with Variations through System-Level Design. VLSI Design 2009: 581-586 - 2008
- [j46]Chong Zhao, Yi Zhao, Sujit Dey:
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 714-724 (2008) - [j45]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1413-1426 (2008) - 2007
- [j44]Chong Zhao, Xiaoliang Bai, Sujit Dey:
Evaluating Transient Error Effects in Digital Nanometer Circuits. IEEE Trans. Reliab. 56(3): 381-391 (2007) - [j43]Naomi Ramos, Debashis Panigrahi, Sujit Dey:
Dynamic adaptation policies to improve quality of service of real-time multimedia applications in IEEE 802.11e WLAN Networks. Wirel. Networks 13(4): 511-535 (2007) - [c106]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations. DAC 2007: 877-882 - [c105]Shoubhik Mukhopadhyay, Curt Schurgers, Sujit Dey:
Joint Computation and Communication Scheduling to Enable Rich Mobile Applications. GLOBECOM 2007: 2117-2122 - [c104]Chong Zhao, Sujit Dey:
Modeling soft error effects considering process variations. ICCD 2007: 376-381 - [c103]Naomi Ramos, Sujit Dey:
A Device and Network-Aware Scaling Framework for Efficient Delivery of Scalable Video over Wireless Networks. PIMRC 2007: 1-5 - 2006
- [c102]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE 2006: 728-733 - [c101]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Considering process variations during system-level power analysis. ISLPED 2006: 342-345 - [c100]Chong Zhao, Sujit Dey:
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). ISQED 2006: 133-140 - [c99]Chong Zhao, Sujit Dey:
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits. ITC 2006: 1-10 - 2005
- [j42]Chong Zhao, Sujit Dey, Xiaoliang Bai:
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. IEEE Des. Test Comput. 22(4): 362-375 (2005) - [j41]Naomi Ramos, Debashis Panigrahi, Sujit Dey:
Quality of service provisioning in 802.11e networks: challenges, approaches, and future directions. IEEE Netw. 19(4): 14-20 (2005) - [c98]Chong Zhao, Yi Zhao, Sujit Dey:
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. DAC 2005: 190-195 - [c97]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC 2005: 571-574 - [c96]Saumya Chandra, Sujit Dey:
Addressing Computational and Networking Constraints to Enable Video Streaming from Wireless Appliances. ESTIMedia 2005: 27-32 - [c95]Chong Zhao, Xiaoliang Bai, Sujit Dey:
A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. ITC 2005: 10 - [c94]Dong-Gi Lee, Sujit Dey:
Dynamic end-to-end image adaptation for guaranteed quality of service in wireless image data services. WCNC 2005: 2512-2518 - 2004
- [j40]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 33-49 (2004) - [j39]Jennifer L. Wong, Miodrag Potkonjak, Sujit Dey:
Optimizing designs using the addition of deflection operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 50-59 (2004) - [j38]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 620-636 (2004) - [j37]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient power profiling for battery-driven embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 919-932 (2004) - [j36]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Design space exploration for optimizing on-chip communication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 952-961 (2004) - [j35]Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1010-1019 (2004) - [j34]Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1256-1263 (2004) - [j33]Xiaoliang Bai, Sujit Dey:
High-level crosstalk defect Simulation methodology for system-on-chip interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1355-1361 (2004) - [j32]Yi Zhao, Sujit Dey, Li Chen:
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 746-755 (2004) - [c93]Chong Zhao, Xiaoliang Bai, Sujit Dey:
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. DAC 2004: 894-899 - [c92]Clark N. Taylor, Sujit Dey:
VSHAPER: an efficient method of serving video streams shaped for diverse wireless communication conditions. GLOBECOM 2004: 4066-4070 - [c91]Clark N. Taylor, Sujit Dey:
Run-time allocation of buffer resources for maximizing video clip quality in a wireless last-hop system. ICC 2004: 3081-3085 - [c90]Debashis Panigrahi, Sujit Dey:
CHASER: content and channel aware object scheduling and error control for wireless Web access in 3G networks. PIMRC 2004: 2119-2123 - [c89]Dong-Gi Lee, Sujit Dey:
Dynamic image adaptation technique and architecture to enhance server performance in wireless image services. PIMRC 2004: 3030-3035 - [c88]Shoubhik Mukhopadhyay, Debashis Panigrahi, Sujit Dey:
Model based error correction for wireless sensor networks. SECON 2004: 575-584 - [c87]Krishna Sekar, Kanishka Lahiri, Sujit Dey:
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. VLSI Design 2004: 307- - [c86]Shoubhik Mukhopadhyay, Debashis Panigrahi, Sujit Dey:
Data aware, low cost error correction for wireless sensor networks. WCNC 2004: 2492-2497 - 2003
- [j31]Krishna Sekar, Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. J. Electron. Test. 19(2): 113-123 (2003) - [j30]Yi Zhao, Sujit Dey:
Fault-coverage analysis techniques of crosstalk in chip interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 770-782 (2003) - [j29]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 538-557 (2003) - [c85]Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey:
A scalable software-based self-test methodology for programmable processors. DAC 2003: 548-553 - [c84]Dong-Gi Lee, Sujit Dey:
Addressing Server Latency and Capacity to Enable Fast and Affordable Wireless Image Data Services. ESTIMedia 2003: 40-47 - [c83]Xiaoliang Bai, Li Chen, Sujit Dey:
Software-based self-test methodology for crosstalk faults in processors. HLDVT 2003: 11-16 - [c82]Krishna Sekar, Kanishka Lahiri, Sujit Dey:
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ICCAD 2003: 641-649 - [c81]Yi Zhao, Sujit Dey:
Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. IOLTS 2003: 7-11 - [c80]Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas:
Noise-Aware Driver Modeling for Nanometer Technology. ISQED 2003: 177-182 - [c79]Xiaoliang Bai, Sujit Dey, Angela Krstic:
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. ITC 2003: 112-121 - [c78]Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design 2003: 467-473 - 2002
- [j28]Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey:
Embedded Software-Based Self-Test for Programmable Core-Based Designs. IEEE Des. Test Comput. 19(4): 18-27 (2002) - [j27]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication-Based Power Management. IEEE Des. Test Comput. 19(4): 118-130 (2002) - [j26]Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. J. Electron. Test. 18(4-5): 529-538 (2002) - [j25]Faraydon Karim, Anh Nguyen, Sujit Dey:
An Interconnect Architecture for Networking Systems on Chips. IEEE Micro 22(5): 36-45 (2002) - [j24]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
Cosimulation-based power estimation for system-on-chip design. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 253-266 (2002) - [c77]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast system-level power profiling for battery-efficient system design. CODES 2002: 157-162 - [c76]Li Chen, Sujit Dey:
Software-based diagnosis for processors. DAC 2002: 259-262 - [c75]Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey:
Embedded software-based self-testing for SoC design. DAC 2002: 355-360 - [c74]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication architecture based power management for battery efficient system design. DAC 2002: 691-696 - [c73]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Battery-efficient architecture for an 802.11 MAC processor. ICC 2002: 669-674 - [c72]Dong-Gi Lee, Sujit Dey:
Adaptive and energy efficient wavelet image compression for mobile multimedia data services. ICC 2002: 2484-2490 - [c71]Yi Zhao, Li Chen, Sujit Dey:
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. ITC 2002: 491-499 - [c70]Clark N. Taylor, Debashis Panigrahi, Sujit Dey:
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication. Embedded Processor Design Challenges 2002: 260-273 - [c69]Luciano Lavagno, Sujit Dey, Rajesh K. Gupta:
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 21-23 - [c68]Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. ASP-DAC/VLSI Design 2002: 261-267 - [c67]Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. ASP-DAC/VLSI Design 2002: 553- - [c66]C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim:
Validation and Test of Network Processors and ASICs. VTS 2002: 407-410 - [c65]Krishna Sekar, Sujit Dey:
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. VTS 2002: 417-422 - 2001
- [j23]Li Chen, Sujit Dey:
Software-based self-testing methodology for processor cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 369-380 (2001) - [j22]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 768-783 (2001) - [c64]Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. DAC 2001: 317-320 - [c63]Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. Rao:
On-Chip Communication Architecture for OC-768 Network Processors. DAC 2001: 678-683 - [c62]Clark N. Taylor, Sujit Dey, Yi Zhao:
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. DAC 2001: 754-757 - [c61]Clark N. Taylor, Sujit Dey:
Adaptive image compression for wireless multimedia communication. ICC 2001: 1925-1929 - [c60]Anand Raghunathan, Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. VLSI Design 2001: 9-10 - [c59]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35 - [c58]Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63 - [c57]Xiaoliang Bai, Sujit Dey:
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. VTS 2001: 169-177 - 2000
- [j21]Sujit Dey, Debashis Panigrahi, Li Chen, Clark N. Taylor, Krishna Sekar, Pablo Sanchez:
Using a Soft Core in a SoC Design: Experiences with picoJava. IEEE Des. Test Comput. 17(3): 60-71 (2000) - [j20]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A fast and low-cost testing technique for core-based system-chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 863-877 (2000) - [c56]Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy:
Test challenges for deep sub-micron technologies. DAC 2000: 142-149 - [c55]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518 - [c54]Xiaoliang Bai, Sujit Dey, Janusz Rajski:
Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624 - [c53]Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng:
Embedded hardware and software self-testing methodologies for processor cores. DAC 2000: 625-630 - [c52]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE 2000: 27-34 - [c51]Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
Interface based hardware/software validation of a system-on-chip. HLDVT 2000: 53-58 - [c50]Yervant Zorian, Sujit Dey, Mike Rodgers:
Test of Future System-on-Chips. ICCAD 2000: 392-398 - [c49]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD 2000: 424-430 - [c48]Yi Zhao, Sujit Dey:
Analysis of interconnect crosstalk defect coverage of test sets. ITC 2000: 492-501 - [c47]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design 2000: 530-537 - [c46]Li Chen, Sujit Dey:
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. VTS 2000: 255-262
1990 – 1999
- 1999
- [j19]Yervant Zorian, Erik Jan Marinissen, Sujit Dey:
Testing Embedded-Core-Based System Chips. Computer 32(6): 52-60 (1999) - [j18]Srimat T. Chakradhar, Sujit Dey:
Resynthesis and retiming for optimum partial scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 621-630 (1999) - [j17]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1114-1131 (1999) - [j16]Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1496-1508 (1999) - [j15]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1661-1676 (1999) - [j14]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 7-15 (1999) - [c45]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61 - [c44]Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao:
Fault modeling and simulation for crosstalk in system-on-chip interconnects. ICCAD 1999: 297-303 - [c43]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD 1999: 566-573 - [c42]Kaushik Roy, Anand Raghunathan, Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips. VLSI Design 1999: 609 - 1998
- [b1]Anand Raghunathan, Niraj K. Jha, Sujit Dey:
High-Level Power Analysis and Optimization. Kluwer 1998, ISBN 978-0-7923-8073-3, pp. I-XVI, 1-157 - [j13]Sujit Dey, Anand Raghunathan, Kenneth D. Wagner:
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. J. Electron. Test. 13(2): 79-91 (1998) - [j12]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13(2): 201-212 (1998) - [j11]Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
A controller redesign technique to enhance testability of controller-data path circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 157-168 (1998) - [j10]Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. 3(2): 285-307 (1998) - [c41]Sujit Dey, Anand Raghunathan, Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial). ASP-DAC 1998: 205-210 - [c40]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES 1998: 117-121 - [c39]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC 1998: 542-547 - [c38]Sujit Dey, Jacob A. Abraham, Yervant Zorian:
High-level design validation and test. ICCAD 1998: 3 - [c37]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664 - [c36]Yervant Zorian, Erik Jan Marinissen, Sujit Dey:
Testing embedded-core based system chips. ITC 1998: 130-143 - [c35]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19 - [c34]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design 1998: 193-198 - 1997
- [j9]Sujit Dey, Miodrag Potkonjak:
Nonscan design-for-testability techniques using RT-level design information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1488-1506 (1997) - [c33]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434 - [c32]Subhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta:
An RTL methodology to enable low overhead combinational testing. ED&TC 1997: 146-152 - [c31]Sujit Dey, Surendra Bommu:
Performance analysis of a system of communicating processes. ICCAD 1997: 590-597 - [c30]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC 1997: 50-59 - [c29]Toshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey:
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs. ITC 1997: 265-274 - 1996
- [j8]Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Fast true delay estimation during high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1088-1105 (1996) - [c28]Kenneth D. Wagner, Sujit Dey:
High-Level Synthesis for Testability: A Survey and Perspective. DAC 1996: 131-136 - [c27]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Glitch Analysis and Reduction in Register Transfer Level. DAC 1996: 331-336 - [c26]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption. ICCAD 1996: 158-165 - [c25]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304 - [c24]Subhrajit Bhattacharya, Sujit Dey:
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. VTS 1996: 74-80 - 1995
- [j7]Sujit Dey, Srimat T. Chakradhar:
Design of testable sequential circuits by repositioning flip-flops. J. Electron. Test. 7(1-2): 105-114 (1995) - [j6]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 531-546 (1995) - [j5]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1067-1075 (1995) - [j4]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1141-1154 (1995) - [c23]Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
Synthesis-for-testability using transformations. ASP-DAC 1995 - [c22]Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi:
Design-for-debugging of application specific designs. ICCAD 1995: 295-301 - [c21]Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
A controller-based design-for-testability technique for controller-data path circuits. ICCAD 1995: 534-540 - 1994
- [c20]Srimat T. Chakradhar, Sujit Dey:
Resynthesis and Retiming for Optimum Partial Scan. DAC 1994: 87-93 - [c19]Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Clock Period Optimization During Resource Sharing and Assignment. DAC 1994: 195-200 - [c18]Miodrag Potkonjak, Sujit Dey:
Optimizing Resource Utilization and Testability Using Hot Potato Techniques. DAC 1994: 201-205 - [c17]Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC 1994: 491-496 - [c16]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Behavioral synthesis of low-cost partial scan designs for DSP applications. ICASSP (2) 1994: 441-444 - [c15]Sujit Dey, Miodrag Potkonjak:
Non-scan design-for-testability of RT-level data paths. ICCAD 1994: 640-645 - [c14]Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Provably correct high-level timing analysis without path sensitization. ICCAD 1994: 736-742 - [c13]Sujit Dey, Miodrag Potkonjak:
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs. ITC 1994: 184-193 - [c12]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application. VTS 1994: 2-7 - [c11]Sujit Dey, Srimat T. Chakradhar:
Retiming sequential circuits to enhance testability. VTS 1994: 28-33 - 1993
- [j3]Subhrajit Bhattacharya, Franc Brglez, Sujit Dey:
Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 304-318 (1993) - [c10]Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
Sequential Circuit Delay optimization Using Global Path Delays. DAC 1993: 483-489 - [c9]Zia Iqbal, Miodrag Potkonjak, Sujit Dey, Alice C. Parker:
Critical Path Minimization Using Retiming and Algebraic Speed-Up. DAC 1993: 573-577 - [c8]Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy:
Exploiting hardware sharing in high-level synthesis for partial scan optimization. ICCAD 1993: 20-25 - [c7]Miodrag Potkonjak, Sujit Dey, Zia Iqbal, Alice C. Parker:
High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. ICCD 1993: 498-504 - 1992
- [c6]Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler:
Performance optimization of sequential circuits by eliminating retiming bottlenecks. ICCAD 1992: 504-509 - [c5]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD 1992: 510-517 - 1991
- [j2]Sujit Dey, Franc Brglez, Gershon Kedem:
Circuit partitioning for logic synthesis. IEEE J. Solid State Circuits 26(3): 350-363 (1991) - [c4]Sujit Dey, Franc Brglez, Gershon Kedem:
Partitioning Sequential Circuits for Logic Optimization. ICCD 1991: 70-76 - [c3]Sujit Dey, Franc Brglez, Gershon Kedem:
Identification and Resynthesis of Pipelines in Sequential Networks. VLSI 1991: 439-449 - 1990
- [j1]Sujit Dey, Pradip K. Srimani:
A New Parallel Sorting Algorithm and its Efficient VLSI Implementation. Comput. J. 33(3): 241-246 (1990) - [c2]Sujit Dey, Franc Brglez, Gershon Kedem:
Corolla Based Circuit Partitioning and Resynthesis. DAC 1990: 607-612
1980 – 1989
- 1988
- [c1]Sujit Dey, Pradip K. Srimani:
Parallel VLSI computation of all shortest paths in a graph. ACM Conference on Computer Science 1988: 373-379
Coauthor Index
[c156] [j81] [c153] [j64] [j57] [j56] [c128] [c126] [j51] [c118] [c117] [c111] [j50] [j47] [c107] [j45] [c106] [c102] [c101] [c97] [j40] [j38] [j37] [j36] [j35] [j29] [c85] [c78] [j27] [j24] [c77] [c74] [c73] [c68] [j22] [c60] [c59] [c58] [c55] [c52] [c49] [c47] [j17] [j16] [j14] [c45] [c43] [c42] [b1] [j13] [c41] [c40] [c37] [c35] [c33] [c27] [c26] [c25]
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