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Mark A. Horowitz
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- affiliation: Stanford University, Department of Electrical Engineering, CA, USA
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2020 – today
- 2024
[j104]Kathleen Feng
, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina:
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. IEEE J. Solid State Circuits 59(3): 947-959 (2024)- [j103]Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina:
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3055-3067 (2024) - [c146]Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina:
Onyx: A Programmable Accelerator for Sparse Tensor Algebra. HCS 2024: 1-91 - [c145]Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz:
Vision Transformer Computation and Resilience for Dynamic Inference. ISPASS 2024: 192-204 - [c144]Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina:
Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j102]Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina:
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays. IEEE Comput. Archit. Lett. 22(1): 45-48 (2023) - [j101]Michelle Reddy, Júlio C. Nardelli, Yuri L. Pereira, Leonardo B. Oliveira, Thiago H. Silva, Marisa Vasconcelos, Mark Horowitz:
Higher education's influence on social networks and entrepreneurship in Brazil. Soc. Netw. Anal. Min. 13(1): 2 (2023) - [j100]Qiaoyi Liu, Jeff Setter, Dillon Huff, Maxwell Strange, Kathleen Feng, Mark Horowitz, Priyanka Raina, Fredrik Kjolstad:
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators. ACM Trans. Archit. Code Optim. 20(2): 26:1-26:26 (2023) - [j99]Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark W. Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina:
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers. ACM Trans. Embed. Comput. Syst. 22(2): 35:1-35:34 (2023) - [j98]Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina:
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains. ACM Trans. Reconfigurable Technol. Syst. 16(2): 26:1-26:28 (2023) - [c143]Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Ritvik Sharma, Clark W. Barrett, Mark A. Horowitz, Pat Hanrahan, Priyanka Raina:
APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis. ASPLOS (3) 2023: 33-45 - [c142]Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjølstad:
The Sparse Abstract Machine. ASPLOS (3) 2023: 710-726 - [i26]Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz, Christopher Torng:
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays. CoRR abs/2301.00861 (2023) - [i25]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. CoRR abs/2306.09552 (2023) - 2022
- [j97]Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, Mark Horowitz:
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2223-2236 (2022) - [j96]Kavya Sreedhar, Mark Horowitz, Christopher Torng:
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4): 163-187 (2022) - [c141]Keyi Zhang, Zain Asgar, Mark Horowitz:
Bringing source-level debugging frameworks to hardware generators. DAC 2022: 1171-1176 - [c140]Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng:
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. DAC 2022: 1339-1342 - [c139]Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina:
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration. HCS 2022: 1-30 - [c138]Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina:
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. VLSI Technology and Circuits 2022: 70-71 - [i24]Keyi Zhang, Zain Asgar, Mark Horowitz:
Bringing Source-Level Debugging Frameworks to Hardware Generators. CoRR abs/2203.05742 (2022) - [i23]Olivia Hsu, Maxwell Strange, Jaeyeon Won, Ritvik Sharma, Kunle Olukotun, Joel S. Emer, Mark Horowitz, Fredrik Kjolstad:
The Sparse Abstract Machine. CoRR abs/2208.14610 (2022) - [i22]Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina:
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays. CoRR abs/2211.13182 (2022) - [i21]Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina:
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays. CoRR abs/2211.17207 (2022) - [i20]Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz:
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications. CoRR abs/2212.02687 (2022) - 2021
- [c137]Nestan Tsiskaridze, Maxwell Strange, Makai Mann, Kavya Sreedhar, Qiaoyi Liu, Mark Horowitz, Clark W. Barrett:
Automating System Configuration. FMCAD 2021: 102-111 - [i19]Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Clark W. Barrett, Mark Horowitz, Pat Hanrahan, Priyanka Raina:
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis. CoRR abs/2104.14155 (2021) - [i18]Qiaoyi Liu, Dillon Huff, Jeff Setter, Maxwell Strange, Kathleen Feng, Kavya Sreedhar, Ziheng Wang, Keyi Zhang, Mark Horowitz, Priyanka Raina, Fredrik Kjolstad:
Compiling Halide Programs to Push-Memory Accelerators. CoRR abs/2105.12858 (2021) - [i17]Nestan Tsiskaridze, Maxwell Strange, Makai Mann, Kavya Sreedhar, Qiaoyi Liu, Mark Horowitz, Clark W. Barrett:
Automating System Configuration. CoRR abs/2108.05987 (2021) - [i16]Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng:
Enabling Reusable Physical Design Flows with Modular Flow Generators. CoRR abs/2111.14535 (2021) - [i15]Kavya Sreedhar, Mark Horowitz, Christopher Torng:
Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions. IACR Cryptol. ePrint Arch. 2021: 1292 (2021) - 2020
- [c136]Xuan Yang, Mingyu Gao, Qiaoyi Liu, Jeff Setter, Jing Pu, Ankita Nayak, Steven Bell, Kaidi Cao, Heonjae Ha, Priyanka Raina, Christos Kozyrakis, Mark Horowitz:
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators. ASPLOS 2020: 369-383 - [c135]Lenny Truong, Steven Herbst, Rajsekhar Setaluri, Makai Mann, Ross G. Daly, Keyi Zhang, Caleb Donovick, Daniel Stanley, Mark Horowitz, Clark W. Barrett, Pat Hanrahan:
fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components. CAV (1) 2020: 403-414 - [c134]Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang:
Creating an Agile Hardware Design Flow. DAC 2020: 1-6 - [c133]Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina:
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs. DATE 2020: 846-851 - [c132]Sneha D. Goenka, Yatish Turakhia, Benedict Paten, Mark Horowitz:
SegAlign: a scalable GPU-based whole genome aligner. SC 2020: 39 - [c131]Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz:
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. VLSI Circuits 2020: 1-2 - [i14]Steven Herbst, ByongChan Lim, Mark Horowitz:
Fast FPGA emulation of analog dynamics in digitally-driven systems. CoRR abs/2002.02072 (2020) - [i13]Lenny Truong, Steven Herbst, Rajsekhar Setaluri, Makai Mann, Ross G. Daly, Keyi Zhang, Caleb Donovick, Daniel Stanley, Mark Horowitz, Clark W. Barrett, Pat Hanrahan:
fault: A Python Embedded Domain-Specific Language For Metaprogramming Portable Hardware Verification Components. CoRR abs/2006.11669 (2020) - [i12]Sung-Jin Kim, Zachary Myers, Steven Herbst, ByongChan Lim, Mark Horowitz:
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator. CoRR abs/2009.09077 (2020)
2010 – 2019
- 2019
- [j95]ByongChan Lim, Mark Horowitz:
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 193-204 (2019) - [c130]Mingyu Gao, Xuan Yang, Jing Pu, Mark Horowitz, Christos Kozyrakis:
TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators. ASPLOS 2019: 807-820 - [c129]Kentaro Yoshioka, Edward Lee, Simon Wong, Mark Horowitz:
Dataset Culling: Towards Efficient Training of Distillation-Based Domain Specific Models. ICIP 2019: 3237-3241 - [c128]Kevin Kiningham, Philip Alexander Levis, Mark Anderson, Dan Boneh, Mark Horowitz, Maurice Shih:
Falcon - A Flexible Architecture For Accelerating Cryptography. MASS 2019: 136-144 - [i11]Kentaro Yoshioka, Edward Lee, Simon Wong, Mark Horowitz:
Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models. CoRR abs/1902.00173 (2019) - [i10]Michelle Reddy, Júlio C. Nardelli, Yuri L. Pereira, Marisa Vasconcelos, Thiago Henrique Silva, Leonardo B. Oliveira, Mark Horowitz:
StartupBR: Higher Education's Influence on Social Networks and Entrepreneurship in Brazil. CoRR abs/1904.12026 (2019) - 2018
- [b1]Steven Bell, Jing Pu, James Hegarty, Mark Horowitz:
Compiling Algorithms for Heterogeneous Systems. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2018, ISBN 978-3-031-00055-3 - [j94]Jing Xiong, Jing Ren, Liqun Luo, Mark Horowitz:
Mapping Histological Slice Sequences to the Allen Mouse Brain Atlas Without 3D Reconstruction. Frontiers Neuroinformatics 12: 93 (2018) - [c127]Steven Herbst, ByongChan Lim, Mark Horowitz:
Fast FPGA emulation of analog dynamics in digitally-driven systems. ICCAD 2018: 131 - [c126]Holly Chiang, James Hong, Kevin Kiningham, Laurynas Riliskis, Philip Alexander Levis, Mark Horowitz:
Tethys: Collecting Sensor Data without Infrastracture or Trust. IoTDI 2018: 249-254 - [i9]Xuan Yang, Mingyu Gao, Jing Pu, Ankita Nayak, Qiaoyi Liu, Steven Bell, Jeff Setter, Kaidi Cao, Heonjae Ha, Christos Kozyrakis, Mark Horowitz:
DNN Dataflow Choice Is Overrated. CoRR abs/1809.04070 (2018) - [i8]Kentaro Yoshioka, Edward Lee, Mark Horowitz:
Training Domain Specific Models for Energy-Efficient Object Detection. CoRR abs/1811.02689 (2018) - 2017
- [j93]Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test 34(2): 39-50 (2017) - [j92]Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, Mark Horowitz:
Programming Heterogeneous Systems from an Image Processing DSL. ACM Trans. Archit. Code Optim. 14(3): 26:1-26:25 (2017) - [j91]Blaine Rister, Mark A. Horowitz, Daniel L. Rubin:
Volumetric Image Registration From Invariant Keypoints. IEEE Trans. Image Process. 26(10): 4900-4910 (2017) - [c125]Mingyu Gao, Jing Pu, Xuan Yang, Mark Horowitz, Christos Kozyrakis:
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory. ASPLOS 2017: 751-764 - 2016
- [j90]Kahye Song, Mark Horowitz:
Tomographic Reconstruction and Alignment Using Matrix Norm Minimization. IEEE J. Sel. Top. Signal Process. 10(1): 47-60 (2016) - [j89]ByongChan Lim, Mark Horowitz:
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 23-33 (2016) - [j88]James Hegarty, Ross G. Daly, Zachary DeVito, Mark Horowitz, Pat Hanrahan, Jonathan Ragan-Kelley:
Rigel: flexible multi-rate image processing hardware. ACM Trans. Graph. 35(4): 85:1-85:11 (2016) - [c124]Kevin Kiningham, Mark Horowitz, Philip Alexander Levis, Dan Boneh:
CESEL: Securing a Mote for 20 Years. EWSN 2016: 307-312 - [c123]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally:
Deep compression and EIE: Efficient inference engine on compressed deep neural network. Hot Chips Symposium 2016: 1-6 - [c122]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
EIE: Efficient Inference Engine on Compressed Deep Neural Network. ISCA 2016: 243-254 - [c121]Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Improving energy efficiency of DRAM by exploiting half page row access. MICRO 2016: 27:1-27:12 - [c120]Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Evaluating programmable architectures for imaging and vision applications. MICRO 2016: 52:1-52:13 - [c119]Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz:
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture. VLSI Circuits 2016: 1-2 - [i7]Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally:
EIE: Efficient Inference Engine on Compressed Deep Neural Network. CoRR abs/1602.01528 (2016) - [i6]Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR abs/1602.04183 (2016) - [i5]Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz:
A Systematic Approach to Blocking Convolutional Neural Networks. CoRR abs/1606.04209 (2016) - [i4]Jing Pu, Sameh Galal, Xuan Yang, Ofer Shacham, Mark Horowitz:
FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI. CoRR abs/1606.07852 (2016) - [i3]Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, Mark Horowitz:
Programming Heterogeneous Systems from an Image Processing DSL. CoRR abs/1610.09405 (2016) - 2015
- [j87]Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark Horowitz:
Convolution engine: balancing efficiency and flexibility in specialized computing. Commun. ACM 58(4): 85-93 (2015) - [j86]ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz:
Digital Analog Design: Enabling Mixed-Signal System Validation. IEEE Des. Test 32(1): 44-52 (2015) - [j85]Stephen Richardson, Dejan Markovic, Andrew Danowitz, John S. Brunhaver, Mark Horowitz:
Building Conflict-Free FFT Schedules. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1146-1155 (2015) - [c118]Blaine Rister, Daniel Reiter, Hejia Zhang, Daniel Volz, Mark Horowitz, Refaat E. Gabr, Joseph R. Cavallaro:
Scale- and orientation-invariant keypoints in higher-dimensional data. ICIP 2015: 3490-3494 - [c117]Holly Chiang, James Hong, Kevin Kiningham, Jiaqi Xue, Laurynas Riliskis, Philip Alexander Levis, Mark Horowitz:
Demo: Tethys - An Energy Harvesting Networked Water Flow Sensor. SenSys 2015: 489-490 - 2014
- [j84]Sabrina Liao, Mark Horowitz:
A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2229-2235 (2014) - [j83]James Hegarty, John S. Brunhaver, Zachary DeVito, Jonathan Ragan-Kelley, Noy Cohen, Steven Bell, Artem Vasilyev, Mark Horowitz, Pat Hanrahan:
Darkroom: compiling high-level image processing code into hardware pipelines. ACM Trans. Graph. 33(4): 144:1-144:11 (2014) - [c116]Mark Horowitz:
1.1 Computing's energy problem (and what we can do about it). ISSCC 2014: 10-14 - 2013
- [c115]Glen Gibb, George Varghese, Mark Horowitz, Nick McKeown:
Design principles for packet parsers. ANCS 2013: 13-24 - [c114]Sameh Galal, Ofer Shacham, John S. Brunhaver, Jing Pu, Artem Vassiliev, Mark Horowitz:
FPU Generator for Design Space Exploration. IEEE Symposium on Computer Arithmetic 2013: 25-34 - [c113]Sabrina Liao, Mark Horowitz:
A Verilog piecewise-linear analog behavior model for mixed-signal validation. CICC 2013: 1-5 - [c112]Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark A. Horowitz:
Convolution engine: balancing efficiency & flexibility in specialized computing. ISCA 2013: 24-35 - [c111]Pat Bosshart, Glen Gibb, Hun-Seok Kim, George Varghese, Nick McKeown, Martin Izzard, Fernando A. Mujica, Mark Horowitz:
Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN. SIGCOMM 2013: 99-110 - [c110]Stephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz:
An area-efficient minimum-time FFT schedule using single-ported memory. VLSI-SoC 2013: 39-44 - 2012
- [j82]Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz:
CPU DB: recording microprocessor history. Commun. ACM 55(4): 55-63 (2012) - [j81]Andrew Adams, David E. Jacobs, Jennifer Dolson, Marius Tico, Kari Pulli, Eino-Ville Talvala, Boris Ajdin, Daniel A. Vaquero, Hendrik P. A. Lensch, Mark Horowitz, Sung Hee Park, Natasha Gelfand, Jongmin Baek, Wojciech Matusik, Marc Levoy:
The Frankencamera: an experimental platform for computational photography. Commun. ACM 55(11): 90-98 (2012) - [j80]Megan Wachs, Ofer Shacham, Zain Asgar, Amin Firoozshahian, Stephen Richardson, Mark Horowitz:
Bringing up a chip on the cheap. IEEE Des. Test 29(6): 57-65 (2012) - [j79]Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz:
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography. IEEE J. Solid State Circuits 47(4): 1031-1042 (2012) - [j78]Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz:
CPU DB: Recording Microprocessor History. ACM Queue 10(4): 10 (2012) - [c109]Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry T. Pileggi, Franz Franchetti:
Design Automation Framework for Application-Specific Logic-in-Memory Blocks. ASAP 2012: 125-132 - [c108]Ofer Shacham, Sameh Galal, Sabarish Sankaranarayanan, Megan Wachs, John S. Brunhaver, Artem Vassiliev, Mark Horowitz, Andrew Danowitz, Wajahat Qadeer, Stephen Richardson:
Avoiding game over: bringing design to the next level. DAC 2012: 623-629 - [c107]Kyle Kelley, Megan Wachs, John P. Stevenson, Stephen Richardson, Mark Horowitz:
Removing overhead from high-level interfaces. DAC 2012: 783-789 - [c106]John P. Stevenson, Amin Firoozshahian, Alex Solomatnikov, Mark Horowitz, David R. Cheriton:
Sparse matrix-vector multiply on the HICAMP architecture. ICS 2012: 195-204 - [c105]Krishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz:
Towards energy-proportional datacenter memory with mobile DRAM. ISCA 2012: 37-48 - [c104]Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo, Benjamin C. Lee, Mark Horowitz:
Rethinking DRAM Power Modes for Energy Proportionality. MICRO 2012: 131-142 - [c103]Hamid Partovi, Alfred Yeung, Luca Ravezzi, Mark Horowitz:
A 3-stage Pseudo Single-phase Flip-flop family. VLSIC 2012: 172-173 - 2011
- [j77]Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
Understanding sources of ineffciency in general-purpose chips. Commun. ACM 54(10): 85-93 (2011) - [j76]Sameh Galal, Mark Horowitz:
Energy-Efficient Floating-Point Unit Design. IEEE Trans. Computers 60(7): 913-922 (2011) - [c102]Sameh Galal, Mark Horowitz:
Latency Sensitive FMA Design. IEEE Symposium on Computer Arithmetic 2011: 129-138 - [c101]Douglas Densmore, Mark Horowitz, Smita Krishnaswamy, Xiling Shen, Adam P. Arkin, Erik Winfree, Chris Voigt:
Joint DAC/IWBDA special session design and synthesis of biological circuits. DAC 2011: 114-115 - [c100]Sangho Youn, Jaeha Kim, Mark Horowitz:
Global convergence analysis of mixed-signal systems. DAC 2011: 498-503 - [c99]Kyle Kelley, Megan Wachs, Andrew Danowitz, P. Stevenson, Stephen Richardson, Mark Horowitz:
Intermediate representations for controllers in chip generators. DATE 2011: 1394-1399 - [c98]Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31 - 2010
- [j75]Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz:
Rethinking Digital Design: Why Design Must Change. IEEE Micro 30(6): 9-24 (2010) - [j74]Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1746-1755 (2010) - [j73]Andrew Adams, David E. Jacobs, Jennifer Dolson, Marius Tico, Kari Pulli, Eino-Ville Talvala, Boris Ajdin, Daniel A. Vaquero, Hendrik P. A. Lensch, Mark Horowitz, Sung Hee Park, Natasha Gelfand, Jongmin Baek, Wojciech Matusik, Marc Levoy:
The Frankencamera: an experimental platform for computational photography. ACM Trans. Graph. 29(4): 29:1-29:12 (2010) - [c97]Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao:
Fortifying analog models with equivalence checking and coverage analysis. DAC 2010: 425-430 - [c96]ByongChan Lim, Jaeha Kim, Mark A. Horowitz:
An efficient test vector generation for checking analog/mixed-signal functional models. DAC 2010: 767-772 - [c95]Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz:
An integrated framework for joint design space exploration of microarchitecture and circuits. DATE 2010: 250-255 - [c94]Mark Horowitz:
Why design must change: Rethinking digital design. DATE 2010: 791 - [c93]Metha Jeeradit, Jaeha Kim, Mark Horowitz:
Intent-leveraged optimization of analog circuits via homotopy. DATE 2010: 1614-1619 - [c92]Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz:
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. ISCA 2010: 26-36 - [c91]Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
Understanding sources of inefficiency in general-purpose chips. ISCA 2010: 37-47
2000 – 2009
- 2009
- [j72]Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald A. Pellegrino:
Towards an explanatory and computational theory of scientific discovery. J. Informetrics 3(3): 191-209 (2009) - [j71]Bita Nezamfar, Elad Alon, Mark Horowitz:
Energy-Performance Tunable Logic. IEEE J. Solid State Circuits 44(9): 2554-2567 (2009) - [j70]Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz:
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design. SIGARCH Comput. Archit. News 37(2): 56-65 (2009) - [c90]Bita Nezamfar, Mark Horowitz:
Energy-performance tunable logic. CICC 2009: 183-186 - [c89]Jaeha Kim, Metha Jeeradit, ByongChan Lim, Mark A. Horowitz:
Leveraging designer's intent: A path toward simpler analog CAD tools. CICC 2009: 613-620 - [c88]Jaeha Kim, Jihong Ren, Mark A. Horowitz:
Stochastic steady-state and AC analyses of mixed-signal systems. DAC 2009: 376-381 - [c87]Bita Nezamfar, Mark Horowitz:
In field, energy-performance tunable FPGA architectures. FPL 2009: 262-267 - [c86]Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
A memory system design framework: creating smart memories. ISCA 2009: 406-417 - [c85]Mark Horowitz:
Why design must change: rethinking digital design. MICRO 2009: 267 - [c84]Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz:
Using a configurable processor generator for computer architecture prototyping. MICRO 2009: 358-369 - [i2]Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald A. Pellegrino:
Towards an explanatory and computational theory of scientific discovery. CoRR abs/0904.1439 (2009) - 2008
- [j69]Mark Horowitz, Don Stark, Elad Alon:
Digital Circuit Design Trends. IEEE J. Solid State Circuits 43(4): 757-761 (2008) - [j68]Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz:
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43(4): 999-1009 (2008) - [j67]Samuel Palermo, Azita Emami-Neyestanak, Mark Horowitz:
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects. IEEE J. Solid State Circuits 43(5): 1235-1246 (2008) - [j66]Elad Alon, Mark Horowitz:
Integrated Regulation for Energy-Efficient Digital Circuits. IEEE J. Solid State Circuits 43(8): 1795-1807 (2008) - [j65]Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
Comparative evaluation of memory models for chip multiprocessors. ACM Trans. Archit. Code Optim. 5(3): 12:1-12:30 (2008) - [c83]Robert Kunz, Mark Horowitz:
The case for simple, visible cache coherency. MSPC 2008: 31-35 - [c82]H. Henry Nho, Mark Horowitz, S. Simon Wong:
A high-speed, low-power 3D-SRAM architecture. CICC 2008: 201-204 - [c81]Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz:
Processor Performance Modeling using Symbolic Simulation. ISPASS 2008: 127-138 - [c80]Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz:
Verification of chip multiprocessor memory systems using a relaxed scoreboard. MICRO 2008: 294-305 - 2007
- [j64]John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz:
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. IEEE J. Solid State Circuits 42(12): 2745-2757 (2007) - [j63]Eino-Ville Talvala, Andrew Adams, Mark Horowitz, Marc Levoy:
Veiling glare in high dynamic range imaging. ACM Trans. Graph. 26(3): 37 (2007) - [c79]Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman:
Robust Energy-Efficient Adder Topologies. IEEE Symposium on Computer Arithmetic 2007: 16-28 - [c78]Elad Alon, Mark Horowitz:
Integrated Regulation for Energy-Efficient Digital Circuits. CICC 2007: 389-392 - [c77]Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz:
Time-Variant Characterization and Compensation of Wideband Circuits. CICC 2007: 487-490 - [c76]Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz:
Chip Multi-Processor Generator. DAC 2007: 262-263 - [c75]Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch. DAC 2007: 440-443 - [c74]Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz:
A new technique for characterization of digital-to-analog converters in high-speed systems. DATE 2007: 433-438 - [c73]Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz:
Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links. ICC 2007: 2693-2698 - [c72]Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Variable domain transformation for linear PAC analysis of mixed-signal systems. ICCAD 2007: 887-894 - [c71]Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
Comparing memory systems for chip multiprocessors. ISCA 2007: 358-368 - [c70]Samuel Palermo, Azita Emami-Neyestanak, Mark Horowitz:
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects. ISSCC 2007: 44-586 - [c69]Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari:
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. ISSCC 2007: 440-614 - [c68]Mark Horowitz:
Scaling, Power and the Future of CMOS. VLSI Design 2007: 23 - 2006
- [j62]Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz:
The implementation of a 2-core, multi-threaded itanium family processor. IEEE J. Solid State Circuits 41(1): 197-209 (2006) - [j61]Elad Alon, Jaeha Kim, Sudhakar Pamarti, Ken Chang, Mark Horowitz:
Replica compensated linear regulators for supply-regulated phase-locked loops. IEEE J. Solid State Circuits 41(2): 413-424 (2006) - [j60]Marc Levoy, Ren Ng, Andrew Adams, Matthew Footer, Mark Horowitz:
Light field microscopy. ACM Trans. Graph. 25(3): 924-934 (2006) - [c67]Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz:
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links. GLOBECOM 2006 - [c66]Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz:
Improving CDR Performance via Estimation. ISSCC 2006: 1296-1303 - 2005
- [j59]Stephen P. Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz:
Digital Circuit Optimization via Geometric Programming. Oper. Res. 53(6): 899-932 (2005) - [j58]Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz:
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(1): 261-275 (2005) - [j57]Elad Alon, Vladimir Stojanovic, Mark A. Horowitz:
Circuits and techniques for high-resolution measurement of on-chip power supply noise. IEEE J. Solid State Circuits 40(4): 820-828 (2005) - [j56]Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, Mark A. Horowitz:
A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer. IEEE J. Solid State Circuits 40(4): 1004-1011 (2005) - [j55]Vladimir Stojanovic, Andrew Ho, Bruno W. Garlepp, Fred Chen, Jason Wei, Grace Tsang, Elad Alon, Ravi T. Kollipara, Carl W. Werner, Jared L. Zerbe, Mark A. Horowitz:
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery. IEEE J. Solid State Circuits 40(4): 1012-1026 (2005) - [j54]Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz:
On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures. Parallel Comput. 31(5): 462-490 (2005) - [j53]Ken Tseng, Mark Horowitz:
False coupling exploration in timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1795-1805 (2005) - [j52]Pradeep Sen, Billy Chen, Gaurav Garg, Stephen R. Marschner, Mark Horowitz, Marc Levoy, Hendrik P. A. Lensch:
Dual photography. ACM Trans. Graph. 24(3): 745-755 (2005) - [j51]Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Eino-Ville Talvala, Emilio R. Antúnez, Adam Barth, Andrew Adams, Mark Horowitz, Marc Levoy:
High performance imaging using large camera arrays. ACM Trans. Graph. 24(3): 765-776 (2005) - [c65]Vaibhav Vaish, Gaurav Garg, Eino-Ville Talvala, Emilio R. Antúnez, Bennett Wilburn, Mark Horowitz, Marc Levoy:
Synthetic Aperture Focusing using a Shear-Warp Factorization of the Viewing Transform. CVPR Workshops 2005: 129 - [c64]Valentin A. Abramzon, Elad Alon, Bita Nezamfar, Mark Horowitz:
Scalable circuits for supply noise measurement. ESSCIRC 2005: 463-466 - [c63]Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd:
A New Method for Design of Robust Digital Circuits. ISQED 2005: 676-681 - 2004
- [j50]Dejan Markovic, Vladimir Stojanovic, Borivoje Nikolic, Mark A. Horowitz, Robert W. Brodersen:
Methods for true energy-performance optimization. IEEE J. Solid State Circuits 39(8): 1282-1293 (2004) - [j49]Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas:
Synthetic aperture confocal imaging. ACM Trans. Graph. 23(3): 825-834 (2004) - [c62]Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz:
The Stream Virtual Machine. IEEE PACT 2004: 267-277 - [c61]Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Marc Levoy, Mark Horowitz:
High-Speed Videography Using a Dense Camera Array. CVPR (2) 2004: 294-301 - [c60]Elad Alon, Vladimir Stojanovic, Joseph M. Kahn, Stephen P. Boyd, Mark Horowitz:
Equalization of modal dispersion in multimode fiber using spatial light modulators. GLOBECOM 2004: 1023-1029 - [c59]Amir Amirkhany, Vladimir Stojanovic, Mark A. Horowitz:
Multi-tone signaling for high-speed backplane electrical links. GLOBECOM 2004: 1111-1117 - [c58]Vladimir Stojanovic, Amir Amirkhany, Mark A. Horowitz:
Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication. ICC 2004: 2799-2806 - 2003
- [j48]Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos:
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits 38(5): 747-754 (2003) - [j47]Frank O'Mahony, C. Patrick Yue, Mark A. Horowitz, S. Simon Wong:
A 10-GHz global clock distribution using coupled standing-wave oscillators. IEEE J. Solid State Circuits 38(11): 1813-1820 (2003) - [j46]Jared L. Zerbe, Carl W. Werner, Vladimir Stojanovic, Fred Chen, Jason Wei, Grace Tsang, Dennis Kim, William F. Stonecypher, Andrew Ho, Timothy P. Thrush, Ravi T. Kollipara, Mark A. Horowitz, Kevin S. Donnelly:
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell. IEEE J. Solid State Circuits 38(12): 2121-2130 (2003) - [j45]Jaeha Kim, Mark A. Horowitz, Gu-Yeon Wei:
Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 860-869 (2003) - [c57]Vladimir Stojanovic, Mark Horowitz:
Modeling and analysis of high-speed links. CICC 2003: 589-594 - [c56]Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang:
Reshaping EDA for power. DAC 2003: 15 - [c55]Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong:
Design of a 10GHz clock distribution network using coupled standing-wave oscillators. DAC 2003: 682-687 - [c54]Dean Liu, Stefanos Sidiropoulos, Mark Horowitz:
A Framework for Designing Reusable Analog Circuits. ICCAD 2003: 375-381 - [c53]Mark Horowitz:
High-Speed Link Design, Then and Now. ICCD 2003 - [c52]Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David A. B. Miller, Mark Horowitz, Olav Solgaard, Nick McKeown:
Scaling internet routers using optics. SIGCOMM 2003: 189-200 - [c51]David Lie, Chandramohan A. Thekkath, Mark Horowitz:
Implementing an untrusted operating system on trusted hardware. SOSP 2003: 178-192 - [c50]David Lie, John C. Mitchell, Chandramohan A. Thekkath, Mark Horowitz:
Specifying and Verifying Hardware for Tamper-Resistant Software. S&P 2003: 166- - 2002
- [j44]Jaeha Kim, Mark A. Horowitz:
An efficient digital sliding controller for adaptive power-supply regulation. IEEE J. Solid State Circuits 37(5): 639-647 (2002) - [j43]Bendik Kleveland, Xiaoning Qi, Liam Madden, Takeshi Furusawa, Robert W. Dutton, Mark A. Horowitz, S. Simon Wong:
High-frequency characterization of on-chip digital interconnects. IEEE J. Solid State Circuits 37(6): 716-725 (2002) - [j42]Jacha Kim, Mark A. Horowitz:
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery. IEEE J. Solid State Circuits 37(11): 1403-1413 (2002) - [c49]Vladimir Marko Stojanovic, Georgios Ginis, Mark A. Horowitz:
Transmit pre-emphasis for high-speed time-division-multiplexed serial-link transceiver. ICC 2002: 1934-1939 - [c48]Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic:
Methods for true power minimization. ICCAD 2002: 35-42 - 2001
- [j41]Bharadwaj S. Amrutur, Mark A. Horowitz:
Fast low-power decoders for RAMs. IEEE J. Solid State Circuits 36(10): 1506-1515 (2001) - [j40]Chih-Kong Ken Yang, Vladimir Stojanovic, Siamak Modjtahedi, Mark A. Horowitz, William F. Ellersick:
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS. IEEE J. Solid State Circuits 36(11): 1684-1692 (2001) - [j39]Ron Ho, Kenneth Mai, Mark A. Horowitz:
The future of wires. Proc. IEEE 89(4): 490-504 (2001) - [c47]Jeff Solomon, Mark Horowitz:
Using Texture Mapping with Mipmapping to Render a VLSI Layout. DAC 2001: 500-505 - [c46]Ghazi Al-Rawi, John M. Cioffi, Rajeev Motwani, Mark Horowitz:
Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures. GLOBECOM 2001: 3012-3018 - [c45]Henrik O. Johansson, Mark Horowitz:
Sampling-rate optimization of an interleaved-sampling front-end. ISCAS (2) 2001: 573-576 - [c44]Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz:
Optimizing the Mapping of Low-Density Parity Check Codes on Parallel Decoding Architectures. ITCC 2001: 578- - 2000
- [j38]Bharadwaj S. Amrutur, Mark A. Horowitz:
Speed and power scaling of SRAM's. IEEE J. Solid State Circuits 35(2): 175-185 (2000) - [j37]Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver. IEEE J. Solid State Circuits 35(5): 757-764 (2000) - [j36]Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz:
A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE J. Solid State Circuits 35(11): 1600-1610 (2000) - [j35]Evelina Yeung, Mark A. Horowitz:
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation. IEEE J. Solid State Circuits 35(11): 1619-1628 (2000) - [c43]David Lie, Chandramohan A. Thekkath, Mark Mitchell, Patrick Lincoln, Dan Boneh, John C. Mitchell, Mark Horowitz:
Architectural Support for Copy and Tamper Resistant Software. ASPLOS 2000: 168-177 - [c42]Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow:
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). DAC 2000: 85 - [c41]Junji Ogawa, Mark Horowitz:
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. Intelligent Memory Systems 2000: 1-14 - [c40]Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz:
Smart Memories: a modular reconfigurable architecture. ISCA 2000: 161-171
1990 – 1999
- 1999
- [j34]Gu-Yeon Wei, Mark Horowitz:
A fully digital, energy-efficient, adaptive power-supply regulator. IEEE J. Solid State Circuits 34(4): 520-528 (1999) - [j33]Ramin Farjad-Rad, Chih-Kong Ken Yang, Mark A. Horowitz, Thomas H. Lee:
A 0.4-μm CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter. IEEE J. Solid State Circuits 34(5): 580-585 (1999) - [j32]Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz:
A portable digital DLL for high-speed CMOS interface circuits. IEEE J. Solid State Circuits 34(5): 632-644 (1999) - [j31]David L. Harris, Mark Horowitz, Dean Liu:
Timing analysis including clock skew. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1608-1618 (1999) - [c39]Jules P. Bergmann, Mark Horowitz:
Vex - A CAD Toolbox. DAC 1999: 523-528 - [c38]Hema Kapadia, Mark Horowitz:
Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology. DAC 1999: 592-597 - [c37]Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz:
Interconnect scaling implications for CAD. ICCAD 1999: 425-429 - [c36]Jules P. Bergmann, Mark Horowitz:
Improving coverage analysis and test generation for large designs. ICCAD 1999: 580-583 - 1998
- [j30]Chih-Kong Ken Yang, Ramin Farjad-Rad, Mark A. Horowitz:
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling. IEEE J. Solid State Circuits 33(5): 713-722 (1998) - [j29]Bharadwaj S. Amrutur, Mark A. Horowitz:
A replica technique for wordline and sense control in low-power SRAM's. IEEE J. Solid State Circuits 33(8): 1208-1219 (1998) - [j28]Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitarai:
Low-power SRAM design using half-swing pulse-mode techniques. IEEE J. Solid State Circuits 33(11): 1659-1671 (1998) - [j27]Arvin Shahani, Derek K. Shaeffer, Sunderarajan S. Mohan, Hirad Samavati, Hamid R. Rategh, Maria del Mar Hershenson, Min Xu, C. Patrick Yue, Daniel J. Eddleman, Mark A. Horowitz, Thomas H. Lee:
Low-power dividerless frequency synthesis using aperture phase detection. IEEE J. Solid State Circuits 33(12): 2232-2239 (1998) - [j26]Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos:
High-speed electrical signaling: overview and limitations. IEEE Micro 18(1): 12-24 (1998) - [j25]Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith:
Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications. ACM Trans. Comput. Syst. 16(2): 170-205 (1998) - [c35]Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz:
Approximate Reachability with BDDs Using Overlapping Projections. DAC 1998: 451-456 - [c34]Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz:
An Evaluation of Directory Schemes for Cache Coherence. 25 Years ISCA: Retrospectives and Reprints 1998: 353-362 - [c33]Jeffrey Kuskin, David Ofelt, Mark A. Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy:
The Stanford FLASH Multiprocessor. 25 Years ISCA: Retrospectives and Reprints 1998: 485-496 - [i1]Nick McKeown, Martin Izzard, Adisak Mekkittikul, Bill Ellersick, Mark Horowitz:
The Tiny Tera: A Packet Switch Core. CoRR cs.NI/9810006 (1998) - 1997
- [j24]Stefanos Sidiropoulos, Mark Horowitz:
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. IEEE J. Solid State Circuits 32(5): 681-690 (1997) - [j23]Ricardo Gonzalez, Benjamin M. Gordon, Mark A. Horowitz:
Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid State Circuits 32(8): 1210-1216 (1997) - [j22]Nobuaki Otsuka, Mark A. Horowitz:
Circuit techniques for 1.5-V power supply flash memory. IEEE J. Solid State Circuits 32(8): 1217-1230 (1997) - [j21]Stefanos Sidiropoulos, Mark A. Horowitz:
A semidigital dual delay-locked loop. IEEE J. Solid State Circuits 32(11): 1683-1692 (1997) - [j20]David L. Harris, Mark A. Horowitz:
Skew-tolerant domino circuits. IEEE J. Solid State Circuits 32(11): 1702-1711 (1997) - [j19]Nick McKeown, Martin Izzard, Adisak Mekkittikul, William Ellersick, Mark Horowitz:
Tiny Tera: a packet switch core. IEEE Micro 17(1): 26-33 (1997) - [j18]Mark A. Heinrich, David Ofelt, Mark A. Horowitz, John L. Hennessy:
Hardware/software co-design of the Stanford FLASH multiprocessor. Proc. IEEE 85(3): 455-466 (1997) - [c32]David L. Harris, Stuart F. Oberman, Mark Horowitz:
SRT Division Architectures and Implementations. IEEE Symposium on Computer Arithmetic 1997: 18-25 - [c31]Dan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz:
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors. ISCA 1997: 73-84 - 1996
- [j17]Ricardo Gonzalez, Mark Horowitz:
Energy dissipation in general purpose microprocessors. IEEE J. Solid State Circuits 31(9): 1277-1284 (1996) - [j16]Chih-Kong Ken Yang, Mark A. Horowitz:
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links. IEEE J. Solid State Circuits 31(12): 2015-2023 (1996) - [c30]Richard C. Ho, Mark Horowitz:
Validation coverage analysis for complex digital designs. ICCAD 1996: 146-151 - [c29]Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith:
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors. ISCA 1996: 260-270 - [c28]Gu-Yeon Wei, Mark Horowitz:
A low power switching power supply for self-clocked systems. ISLPED 1996: 313-317 - [e1]Mark Horowitz, Jan M. Rabaey, Brock Barton, Massoud Pedram:
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996. IEEE 1996, ISBN 0-7803-3571-6 [contents] - 1995
- [j15]Ivo Dobbelaere, Mark Horowitz, Abbas El Gamal:
Regenerative feedback repeaters for programmable interconnections. IEEE J. Solid State Circuits 30(11): 1246-1253 (1995) - [c27]H. Dhanesha, K. Falakshahi, Mark Horowitz:
Array-of-arrays architecture for parallel floating point multiplication. ARVLSI 1995: 150-157 - [c26]Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill:
Architecture Validation for Processors. ISCA 1995: 404-413 - [c25]Kimiyoshi Usami, Mark Horowitz:
Clustered voltage scaling technique for low-power design. ISLPD 1995: 3-8 - 1994
- [j14]Russell Kao, Mark Horowitz:
Eliminating redundant DC equations for asymptotic waveform evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 396-397 (1994) - [j13]Russell Kao, Mark Horowitz:
Timing analysis for piecewise linear Rsim. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1498-1512 (1994) - [j12]Mark E. Dean, David L. Dill, Mark Horowitz:
Self-timed logic using Current-Sensing Completion Detection (CSCD). J. VLSI Signal Process. 7(1-2): 7-16 (1994) - [c24]Mark A. Heinrich, Jeffrey Kuskin, David Ofelt, John Heinlein, Joel Baxter, Jaswinder Pal Singh, Richard Simoni, Kourosh Gharachorloo, David Nakahira, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy:
The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor. ASPLOS 1994: 274-285 - [c23]James Laudon, Anoop Gupta, Mark Horowitz:
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. ASPLOS 1994: 308-318 - [c22]Jeffrey Kuskin, David Ofelt, Mark A. Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy:
The Stanford FLASH Multiprocessor. ISCA 1994: 302-313 - [c21]James A. Gasbarro, Mark Horowitz:
Techniques for Characterizing DRAMs With a 500-MHz Interface. ITC 1994: 516-525 - [p1]James Laudon, Anoop Gupta, Mark Horowitz:
Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors. Multithreaded Computer Architecture 1994: 167-200 - 1993
- [j11]Steven M. Nowick, Mark E. Dean, David L. Dill, Mark Horowitz:
The design of a high-performance cache controller: a case study in asynchronous synthesis. Integr. 15(3): 241-262 (1993) - [c20]Russell Kao, Mark Horowitz:
Piecewise linear models for Rsim. ICCAD 1993: 753-758 - 1992
- [j10]Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica S. Lam:
The Stanford Dash Multiprocessor. Computer 25(3): 63-79 (1992) - [c19]Michael D. Smith, Mark Horowitz, Monica S. Lam:
Efficient Superscalar Performance Through Boosting. ASPLOS 1992: 248-259 - [c18]James Laudon, Anoop Gupta, Mark Horowitz:
Architectural and implementation tradeoffs in the design of multiple-context processors. ISCA 1992: 435 - 1991
- [c17]Ted E. Williams, Mark A. Horowitz:
A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. IEEE Symposium on Computer Arithmetic 1991: 210-217 - [c16]Mark E. Dean, David L. Dill, Mark Horowitz:
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). ICCD 1991: 187-191 - [c15]Richard Simoni, Mark Horowitz:
Modeling the Performance of Limited Pointers Directories for Cache Coherence. ISCA 1991: 309-319 - 1990
- [j9]Don Stark, Mark Horowitz:
Techniques for calculating currents and voltages in VLSI power supply networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 126-132 (1990) - [c14]Daniel Lenoski, Kourosh Gharachorloo, James Laudon, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica Lam:
Design of scalable shared-memory multiprocessors: the DASH approach. Compcon 1990: 62-67 - [c13]Michael D. Smith, Monica S. Lam, Mark Horowitz:
Boosting Beyond Static Scheduling in a Superscalar Processor. ISCA 1990: 344-354
1980 – 1989
- 1989
- [j8]James A. Gasbarro, Mark A. Horowitz:
Integrated pin electronics for VLSI functional testers. IEEE J. Solid State Circuits 24(2): 331-337 (1989) - [j7]Mark R. Santoro, Mark A. Horowitz:
SPIM: a pipelined 64*64-bit iterative multiplier. IEEE J. Solid State Circuits 24(2): 487-493 (1989) - [j6]Anant Agarwal, Mark Horowitz, John L. Hennessy:
An Analytical Cache Model. ACM Trans. Comput. Syst. 7(2): 184-215 (1989) - [c12]Mark R. Santoro, Gary Bewick, Mark A. Horowitz:
Rounding algorithms for IEEE multipliers. IEEE Symposium on Computer Arithmetic 1989: 176-183 - [c11]Michael D. Smith, Mike Johnson, Mark Horowitz:
Limits on Multiple Instruction Issue. ASPLOS 1989: 290-302 - [c10]A. Salz, Mark Horowitz:
IRSIM: An Incremental MOS Switch-Level Simulator. DAC 1989: 173-178 - [c9]Steven A. Przybylski, Mark Horowitz, John L. Hennessy:
Characteristics of Performance-Optimal Multi-Level Cache Hierarchies. ISCA 1989: 114-121 - 1988
- [j5]Karen A. Huyser, Mark A. Horowitz:
Generalization in digital functions. Neural Networks 1(Supplement-1): 101 (1988) - [j4]Anant Agarwal, John L. Hennessy, Mark Horowitz:
Cache Performance of Operating System and Multiprogramming Workloads. ACM Trans. Comput. Syst. 6(4): 393-431 (1988) - [c8]Don Stark, Mark Horowitz:
Analyzing CMOS Power Supply Networks Using Ariel. DAC 1988: 460-464 - [c7]Russell Kao, Bob Alverson, Mark Horowitz, Don Stark:
Bisim: a simulator for custom ECL circuits. ICCAD 1988: 62-65 - [c6]Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz:
An Evaluation of Directory Schemes for Cache Coherence. ISCA 1988: 280-289 - [c5]Steven A. Przybylski, Mark Horowitz, John L. Hennessy:
Performance Tradeoffs in Cache Design. ISCA 1988: 290-298 - 1987
- [j3]Chorng-Yeong Chu, Mark Horowitz:
Charge-Sharing Models for Switch-Level Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1053-1061 (1987) - [c4]Clyde W. Carpenter, Mark Horowitz:
Generating Incremental VLSI Compaction Spacing Constraints. DAC 1987: 291-297 - [c3]Don Stark, Mark Horowitz:
RED: Resistance Extraction for Digital Simulation. DAC 1987: 570-573 - [c2]Paul Chow, Mark Horowitz:
Architectural Tradeoffs in the Design of MIPS-X. ISCA 1987: 300-308 - 1986
- [c1]Anant Agarwal, Richard L. Sites, Mark Horowitz:
ATUM: A New Technique for Capturing Address Traces Using Microcode. ISCA 1986: 119-127 - 1983
- [j2]Mark Horowitz, Robert W. Dutton:
Resistance Extraction from Mask Layout Data. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(3): 145-150 (1983) - [j1]Jorge Rubinstein, Paul Penfield Jr., Mark A. Horowitz:
Signal Delay in RC Tree Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(3): 202-211 (1983)
Coauthor Index
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