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Roy Dz-Ching Ju
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- affiliation: Intel
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2010 – 2019
- 2015
- [j16]Jenq Kuen Lee, Albert Cohen, Roy Ju, Kuan-Ching Li:
Guest Editorial: Embedded Multicore Systems and Applications. J. Signal Process. Syst. 80(3): 241-243 (2015) - 2012
- [j15]Ming-Yu Hung, Peng-Sheng Chen, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee:
Support of Probabilistic Pointer Analysis in the SSA Form. IEEE Trans. Parallel Distributed Syst. 23(12): 2366-2379 (2012) - 2010
- [j14]Dinesh C. Suresh, Roy Ju, Michael Lai, Mei Ye:
Multi-core scalability-impacting compiler optimizations. Comput. Sci. Res. Dev. 25(1-2): 15-24 (2010)
2000 – 2009
- 2007
- [j13]Gilberto Contreras, Margaret Martonosi, Jinzhang Peng, Guei-Yuan Lueh, Roy Ju:
The XTREM power and performance simulator for the Intel XScale core: Design and experiences. ACM Trans. Embed. Comput. Syst. 6(1): 4 (2007) - [c31]Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju:
A Throughput-Driven Task Creation and Mapping for Network Processors. HiPEAC 2007: 227-241 - 2006
- [j12]Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
Recovery code generation for general speculative optimizations. ACM Trans. Archit. Code Optim. 3(1): 67-89 (2006) - 2005
- [c30]Kaiyu Chen, Sun Chan, Roy Dz-Ching Ju, Peng Tu:
Optimizing structures in object oriented programs. Interaction between Compilers and Computer Architectures 2005: 94-103 - [c29]Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Roy Ju:
Optimizing Packet Accesses for a Domain Specific Language on Network Processors. LCPC 2005: 47-61 - [c28]Chen Yang, Yongjian Chen, Xiong Fu, Chu-Cheow Lim, Roy Ju:
POV-Ray Parallelization and Optimization: An Experience Report. PDPTA 2005: 997-1003 - [c27]Michael K. Chen, Xiao-Feng Li, Ruiqi Lian, Jason H. Lin, Lixia Liu, Tao Liu, Roy Ju:
Shangri-La: achieving high performance from compiled network applications while enabling ease of programming. PLDI 2005: 224-236 - 2004
- [j11]Dong-yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu:
Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. J. Instr. Level Parallelism 6 (2004) - [j10]Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
A compiler framework for speculative optimizations. ACM Trans. Archit. Code Optim. 1(3): 247-271 (2004) - [j9]Peng-Sheng Chen, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee:
Interprocedural Probabilistic Pointer Analysis. IEEE Trans. Parallel Distributed Syst. 15(10): 893-907 (2004) - [c26]Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. IEEE PACT 2004: 17-28 - [c25]Chengyong Wu, Ruiqi Lian, Junchao Zhang, Roy Ju, Sun Chan, Lixia Liu, Xiaobing Feng, Zhaoqing Zhang:
An Overview of the Open Research Compiler. LCPC 2004: 17-31 - [c24]Gilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh:
XTREM: a power simulator for the Intel XScale® core. LCTES 2004: 115-125 - 2003
- [j8]Gwan-Hwan Hwang, Cheng-Wei Chen, Jenq Kuen Lee, Roy Dz-Ching Ju:
Segmented Alignment: An Enhanced Model to Align Data Parallel Programs of HPF. J. Supercomput. 25(1): 17-41 (2003) - [c23]Yang Liu, Zhaoqing Zhang, Ruliang Qiao, Roy Dz-Ching Ju:
A Region-Based Compilation Infrastructure. Interaction between Compilers and Computer Architectures 2003: 75-84 - [c22]Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Dz-Ching Ju:
Efficient Resource Management during Instruction Scheduling for the EPIC Architecture. IEEE PACT 2003: 36-45 - [c21]Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang:
Inter-procedural stacked register allocation for itanium® like architecture. ICS 2003: 215-225 - [c20]Youfeng Wu, Li-Ling Chen, Roy Ju, Jesse Fang:
Performance potentials of compiler-directed data speculation. ISPASS 2003: 22-31 - [c19]Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai, Sun Chan:
A compiler framework for speculative analysis and optimizations. PLDI 2003: 289-299 - [c18]Peng-Sheng Chen, Ming-Yu Hung, Yuan-Shin Hwang, Roy Dz-Ching Ju, Jenq Kuen Lee:
Compiler support for speculative multithreading architecture with probabilistic points-to analysis. PPoPP 2003: 25-36 - 2001
- [j7]Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju:
Array Operation Synthesis to Optimize HPF Programs on Distributed Memory Machines. J. Parallel Distributed Comput. 61(4): 467-500 (2001) - [c17]Srikanth T. Srinivasan, Roy Dz-Ching Ju, Alvin R. Lebeck, Chris Wilkerson:
Locality vs. criticality. ISCA 2001: 132-143 - [c16]Yuan-Shin Hwang, Peng-Sheng Chen, Jenq Kuen Lee, Roy Dz-Ching Ju:
Probabilistic Points-to Analysis. LCPC 2001: 290-305 - 2000
- [c15]Roy Dz-Ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu:
A Unified Compiler Framework for Control and Data Speculation. IEEE PACT 2000: 157-168 - [c14]Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank:
Applying Data Speculation in Modulo Scheduled Loops. IEEE PACT 2000: 169-178 - [c13]Jens Knoop, Jean-Francois Collard, Roy Dz-Ching Ju:
Partial Redundancy Elimination on Predicated Code. SAS 2000: 260-279
1990 – 1999
- 1999
- [j6]Roy Dz-Ching Ju, Jean-Francois Collard, Karim Oukbir:
Probabilistic memory disambiguation and its application to data speculation. SIGARCH Comput. Archit. News 27(1): 27-30 (1999) - [c12]Vugranam C. Sreedhar, Roy Dz-Ching Ju, David M. Gillies, Vatsa Santhanam:
Translating Out of Static Single Assignment Form. SAS 1999: 194-210 - 1998
- [j5]Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju:
A Function-Composition Approach to Synthesize Fortran 90 Array Operations. J. Parallel Distributed Comput. 54(1): 1-47 (1998) - [c11]A. V. S. Sastry, Roy Dz-Ching Ju:
A New Algorithm for Scalar Register Promotion based on SSA Form. PLDI 1998: 15-25 - 1997
- [c10]Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju:
Algorithm and Hardware Support for Branch Anticipation. Great Lakes Symposium on VLSI 1997: 163- - [c9]Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju:
Integrating Automatic Data Alignment and Array Operation Synthesis to Optimize Data Parallel Programs. LCPC 1997: 412-415 - 1996
- [c8]Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju:
Array Operation Synthesis to Optimize HPF Programs. ICPP, Vol. 3 1996: 1-8 - [c7]David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker:
Global Predicate Analysis and Its Application to Register Allocation. MICRO 1996: 114-125 - 1995
- [c6]Gwan-Hwan Hwang, Jenq Kuen Lee, Roy Dz-Ching Ju:
An Array Operation Synthesis Scheme to Optimize Fortran 90 Programs. PPoPP 1995: 112-122 - 1994
- [j4]Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini:
The Classification, Fusion, and Parallelization of Array Language Primitives. IEEE Trans. Parallel Distributed Syst. 5(10): 1113-1120 (1994) - [c5]David F. Bacon, Jyh-Herng Chow, Dz-Ching Ju, Kalyan Muthukumar, Vivek Sarkar:
A compiler framework for restructuring data declarations to enhance cache and TLB effectiveness. CASCON 1994: 3 - [c4]Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini:
Statement Merge: an Inter-Statement Optimization of Array Language Programs. ICPP (2) 1994: 126-129 - 1993
- [j3]Wai-Mee Ching, Paul R. Carini, Dz-Ching Ju:
A Primitive-Based Strategy for Producing Efficient Code for Very High Level Programs. Comput. Lang. 19(1): 41-50 (1993) - [j2]Wai-Mee Ching, Dz-Ching Ju:
An APL-to-C compiler for the IBM RISC System/6000: compilation, performance and limitations. ACM SIGAPL APL Quote Quad 23(3): 15-21 (1993) - 1992
- [c3]Dz-Ching Ju, Chuan-lin Wu, Paul R. Carini:
The Synthesis of Array Functions and Its Use in Parallel Computation. ICPP (2) 1992: 293-296 - 1991
- [j1]Wai-Mee Ching, Dz-Ching Ju:
Execution of automatically parallelized APL programs on RP3. IBM J. Res. Dev. 35(5): 767-778 (1991) - [c2]Dz-Ching Ju, Wai-Mee Ching, Chuan-lin Wu:
On Performance and Space Usage Improvements for Parallelized Compiled APL Code. APL 1991: 234-243 - [c1]Dz-Ching Ju, Wai-Mee Ching:
Exploitation of APL Data Parallelism on a Shared-memory MIMD Machine. PPoPP 1991: 61-72
Coauthor Index
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