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ORCIDBipul Chandra Paul
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- affiliation: Purdue University, West Lafayette, USA
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2020 – today
- 2022
[c19]Nishtha S. Gaul, Akhilesh Jaiswal, Hongsik Yoon, Taeyoung Lee
, Kazutaka Yamane, Joseph Versaggi, Rick Carter, Bipul C. Paul:
A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement. IMW 2022: 1-4
2010 – 2019
- 2019
- [j16]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - 2018
- [j15]Bipul C. Paul, Ajey P. Jacob, William Taylor, Randy W. Mann, Joseph Versaggi, Edward J. Nowak, Lars W. Liebmann:
A Retrospective View on the Technology Evolution to Support Low Power Mobile Application. J. Low Power Electron. 14(3): 374-392 (2018) - 2013
- [j14]Bipul C. Paul, Arijit Raychowdhury:
Introduction to the special issue on memory technologies. ACM J. Emerg. Technol. Comput. Syst. 9(2): 10:1-10:2 (2013) - 2011
- [p1]Bipul C. Paul, Arijit Raychowdhury:
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 185-207
2000 – 2009
- 2009
- [j13]Bipul C. Paul, Krishnendu Chakrabarty:
Advances in nanoelectronics circuits and systems [Editorial]. IET Comput. Digit. Tech. 3(6): 551-552 (2009) - [j12]Bipul C. Paul, Shinobu Fujita, Masaki Okajima:
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier. IEEE J. Solid State Circuits 44(11): 2935-2942 (2009) - 2008
- [c18]Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima:
ROM based logic (RBL) design: High-performance and low-power adders. ISCAS 2008: 796-799 - [c17]Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra:
Optimized Circuit Failure Prediction for Aging: Practicality and Promise. ITC 2008: 1-10 - 2007
- [j11]Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee:
Prospect of ballistic CNFET in high performance applications: Modeling and analysis. ACM J. Emerg. Technol. Comput. Syst. 3(3): 12 (2007) - [j10]Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 743-751 (2007) - [c16]Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra:
Circuit Failure Prediction and Its Application to Transistor Aging. VTS 2007: 277-286 - 2006
- [j9]Bipul C. Paul, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electron. Test. 22(2): 115-124 (2006) - [j8]Bipul Chandra Paul, Amit Agarwal, Kaushik Roy:
Low-power design techniques for scaled technologies. Integr. 39(2): 64-89 (2006) - [j7]Aditya Bansal, Bipul Chandra Paul, Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2765-2774 (2006) - [j6]Kunhyuk Kang, Bipul C. Paul, Kaushik Roy:
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006) - [c15]Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee:
Modeling and analysis of circuit performance of ballistic CNFET. DAC 2006: 717-722 - [c14]Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785 - [c13]Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861 - 2005
- [j5]Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy:
Process variation in embedded memories: failure analysis and variation aware architecture. IEEE J. Solid State Circuits 40(9): 1804-1814 (2005) - [j4]Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 27-38 (2005) - [j3]Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1213-1224 (2005) - [c12]Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy:
Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769 - 2004
- [j2]Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy:
Enhancing Yield at the End of the Technology Roadmap. IEEE Des. Test Comput. 21(6): 563-571 (2004) - [c11]Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy:
Adaptive supply voltage technique for low swing interconnects. ASP-DAC 2004: 284-287 - [c10]Amit Agarwal, Bipul C. Paul, Kaushik Roy:
Process variation in nano-scale memories: failure analysis and process tolerant architecture. CICC 2004: 353-356 - [c9]Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC 2004: 454-459 - [c8]Amit Agarwal, Bipul Chandra Paul, Kaushik Roy:
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154 - [c7]Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy:
Device optimization for ultra-low power digital sub-threshold operation. ISLPED 2004: 96-101 - [c6]Bipul Chandra Paul, Cassondra Neau, Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC 2004: 1269-1275 - 2002
- [c5]Bipul Chandra Paul, Kaushik Roy:
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC 2002: 384-390 - [c4]Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Dynamic Noise Analysis with Capacitive and Inductive Coupling. ASP-DAC/VLSI Design 2002: 65-70 - 2001
- [j1]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Robust subthreshold logic for ultra-low power operation. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 90-99 (2001) - [c3]Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy:
Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium 2001: 449- - [c2]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design 2001: 211-214 - 2000
- [c1]Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
Robust ultra-low power sub-threshold DTMOS logic. ISLPED 2000: 25-30
Coauthor Index
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