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ORCIDLawrence T. Pileggi
Larry T. Pileggi – Lawrence T. Pillage
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2020 – today
- 2024
[c200]Christopher Talbot
, Deepali Garg, Lawrence T. Pileggi, Kenneth Mai:
An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. DAC 2024: 103:1-103:6- [c199]Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi:
Quantifying the Efficacy of Logic Locking Methods. VLSID 2024: 541-546 - [i40]Aayushya Agarwal, Larry T. Pileggi, Ronald A. Rohrer:
Second-Order Optimization via Quiescence. CoRR abs/2410.08033 (2024) - [i39]Aayushya Agarwal, Gauri Joshi, Lawrence T. Pileggi:
FedECADO: A Dynamical System Model of Federated Learning. CoRR abs/2410.09933 (2024) - [i38]Aayushya Agarwal, Yihan Ruan, Lawrence T. Pileggi:
A Hybrid Simulation of DNN-based Gray Box Models. CoRR abs/2410.17103 (2024) - 2023
- [c198]Shimiao Li, Ján Drgona, Shrirang Abhyankar, Larry T. Pileggi:
Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning. e-Energy (Companion) 2023: 106-114 - [c197]Brian Singer, Amritanshu Pandey, Shimiao Li, Lujo Bauer, Craig Miller, Lawrence T. Pileggi, Vyas Sekar:
Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations. SP 2023: 38-55 - [i37]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Contingency Analyses with Warm Starter using Probabilistic Graphical Model. CoRR abs/2304.06727 (2023) - [i36]Shimiao Li, Ján Drgona, Shrirang Abhyankar, Larry T. Pileggi:
Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning. CoRR abs/2304.10702 (2023) - [i35]Aayushya Agarwal, Carmel Fiscko, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
An Equivalent Circuit Workflow for Unconstrained Optimization. CoRR abs/2305.14061 (2023) - [i34]Aayushya Agarwal, Larry T. Pileggi:
An Equivalent Circuit Approach to Distributed Optimization. CoRR abs/2305.14607 (2023) - [i33]Carmel Fiscko, Aayushya Agarwal, Yihan Ruan, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
Towards Hyperparameter-Agnostic DNN Training via Dynamical System Insights. CoRR abs/2310.13901 (2023) - [i32]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [c196]Larry T. Pileggi, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Ken Mai, Franz Franchetti:
A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. HPEC 2022: 1-7 - [i31]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Circuit-theoretic Line Outage Distribution Factor. CoRR abs/2204.07684 (2022) - [i30]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Towards Practical Physics-Informed ML Design and Evaluation for Power Grid. CoRR abs/2205.03673 (2022) - [i29]Aayushya Agarwal, Carmel Fiscko, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
ECCO: Equivalent Circuit Controlled Optimization. CoRR abs/2211.08478 (2022) - [i28]Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno:
Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. 2022: 545 (2022) - 2021
- [j61]Samuel Pagliarini, Joseph Sweeney, Ken Mai, R. D. Shawn Blanton, Larry T. Pileggi, Subhasish Mitra:
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38(4): 109-118 (2021) - [c195]Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai:
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. DATE 2021: 1186-1191 - [c194]Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai:
Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA 2021: 1-10 - [c193]Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow. HICSS 2021: 1-10 - [c192]Priya L. Donti, Aayushya Agarwal, Neeraj Vijay Bedmutha, Larry T. Pileggi, J. Zico Kolter:
Adversarially robust learning for security-constrained optimal power flow. NeurIPS 2021: 28677-28689 - [i27]Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi:
Quantifying the Efficacy of Logic Locking Methods. CoRR abs/2103.06990 (2021) - [i26]Aayushya Agarwal, Amritanshu Pandey, Larry T. Pileggi:
Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge. CoRR abs/2103.09853 (2021) - [i25]Naeem Turner-Bandele, Amritanshu Pandey, Larry T. Pileggi:
Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis. CoRR abs/2107.04576 (2021) - [i24]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
A Convex Method of Generalized State Estimation using Circuit-theoretic Node-breaker Model. CoRR abs/2109.14742 (2021) - [i23]Timothy McNamara, Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Two-Stage Homotopy Method to Incorporate Discrete Control Variables into AC-OPF. CoRR abs/2110.07522 (2021) - [i22]Priya L. Donti, Aayushya Agarwal, Neeraj Vijay Bedmutha, Larry T. Pileggi, J. Zico Kolter:
Adversarially Robust Learning for Security-Constrained Optimal Power Flow. CoRR abs/2111.06961 (2021) - [i21]Naeem Turner-Bandele, Amritanshu Pandey, Larry T. Pileggi:
A Risk-Managed Steady-State Analysis to Assess The Impact of Power Grid Uncertainties. CoRR abs/2111.10290 (2021) - [i20]Marko Jereminov, Larry T. Pileggi:
Equivalent Circuit Programming for Power Flow Analysis and Optimization. CoRR abs/2112.01351 (2021) - 2020
- [j60]Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi:
CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. 5(55): 2646 (2020) - [j59]Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi:
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 520-532 (2020) - [j58]Samuel N. Pagliarini, Sudipta Bhuin, Mehmet Meric Isgenc, Ayan Kumar Biswas, Lawrence T. Pileggi:
A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 31(4): 1113-1123 (2020) - [j57]Amritanshu Pandey, Larry T. Pileggi:
Steady-State Simulation for Combined Transmission and Distribution Systems. IEEE Trans. Smart Grid 11(2): 1124-1135 (2020) - [j56]Marko Jereminov, David M. Bromberg, Amritanshu Pandey, Martin R. Wagner, Larry T. Pileggi:
Evaluating Feasibility Within Power Flow. IEEE Trans. Smart Grid 11(4): 3522-3534 (2020) - [j55]Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 585-595 (2020) - [c191]Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. HOST 2020: 132-141 - [c190]Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi:
Modeling Techniques for Logic Locking. ICCAD 2020: 80:1-80:9 - [c189]Shimiao Li, Amritanshu Pandey, Soummya Kar, Larry T. Pileggi:
A Circuit-Theoretic Approach to State Estimation. ISGT-Europe 2020: 1126-1130 - [c188]Joseph Sweeney, Marijn Heule, Lawrence T. Pileggi:
Sensitivity Analysis of Locked Circuits. LPAR 2020: 483-497 - [i19]Joseph Sweeney, Samuel Pagliarini, Lawrence T. Pileggi:
Securing Digital Systems via Split-Chip Obfuscation. CoRR abs/2005.10083 (2020) - [i18]Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. CoRR abs/2005.10649 (2020) - [i17]Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi:
Modeling Techniques for Logic Locking. CoRR abs/2009.10131 (2020) - [i16]Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow. CoRR abs/2011.00587 (2020) - [i15]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach. CoRR abs/2011.06021 (2020) - [i14]Shimiao Li, Amritanshu Pandey, Bryan Hooi, Christos Faloutsos, Larry T. Pileggi:
Dynamic Graph-Based Anomaly Detection in the Electrical Grid. CoRR abs/2012.15006 (2020)
2010 – 2019
- 2019
- [j54]Ioannis Karageorgos, Mehmet Meric Isgenc, Samuel Pagliarini, Lawrence T. Pileggi:
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. J. Hardw. Syst. Secur. 3(4): 382-396 (2019) - [c187]Aayushya Agarwal, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Implicitly Modeling Frequency Control within Power Flow. ISGT Europe 2019: 1-5 - [c186]Aleksandar Jovicic, Marko Jereminov, Larry T. Pileggi, Gabriela Hug:
A Linear Formulation for Power System State Estimation including RTU and PMU Measurements. ISGT Europe 2019: 1-5 - [c185]Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Martin R. Wagner, David M. Bromberg, Larry T. Pileggi:
Robust Sequential Steady-State Analysis of Cascading Outages. ISGT Europe 2019: 1-5 - [c184]Fazle Sadi, Joe Sweeney, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization. MICRO 2019: 347-358 - [i13]Marko Jereminov, Bryan Hooi, Amritanshu Pandey, Hyun Ah Song, Christos Faloutsos, Lawrence T. Pileggi:
Impact of Load Models on Power Flow Optimization. CoRR abs/1902.04154 (2019) - [i12]Amritanshu Pandey, Larry T. Pileggi:
Steady-State Simulation for Combined Transmission and Distribution Systems. CoRR abs/1907.12725 (2019) - [i11]Aayushya Agarwal, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Implicitly Modeling Frequency Control within Power Flow. CoRR abs/1908.11778 (2019) - [i10]Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Larry T. Pileggi:
Robust Online Simulation Framework for Grid Restoration Under Loss of SCADA. CoRR abs/1910.03557 (2019) - [i9]Shimiao Li, Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Larry T. Pileggi:
A LASSO-Inspired Approach for Localizing Power System Infeasibility. CoRR abs/1911.05154 (2019) - [i8]Shimiao Li, Amritanshu Pandey, Soummya Kar, Larry T. Pileggi:
A Circuit-Theoretic Approach to State Estimation. CoRR abs/1911.05155 (2019) - 2018
- [j53]Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes:
Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 458-470 (2018) - [j52]Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi:
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1627-1636 (2018) - [c183]Bryan Hooi, Leman Akoglu, Dhivya Eswaran, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph. CIKM 2018: 507-516 - [c182]Shaolong Liu, Jeyanandh Paramesh, Larry T. Pileggi, Taimur Gibran Rabuske, Jorge Fernandcs:
A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS. ESSCIRC 2018: 22-25 - [c181]Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV. HPEC 2018: 1-7 - [c180]Thomas C. Jackson, Samuel Pagliarini, Lawrence T. Pileggi:
An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. ICRC 2018: 1-7 - [c179]Bryan Hooi, Dhivya Eswaran, Hyun Ah Song, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid. ECML/PKDD (1) 2018: 71-86 - [c178]Bryan Hooi, Hyun Ah Song, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
StreamCast: Fast and Online Mining of Power Grid Time Sequences. SDM 2018: 531-539 - [i7]Amritanshu Pandey, Marko Jereminov, Martin R. Wagner, David M. Bromberg, Gabriela Hug, Larry T. Pileggi:
Robust Steady State Analysis of the Power Grid. CoRR abs/1803.01211 (2018) - [i6]Martin R. Wagner, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Robust Probabilistic Analysis of Transmission Power Systems based on Equivalent Circuit Formulation. CoRR abs/1804.07794 (2018) - 2017
- [c177]Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC 2017: 18:1-18:2 - [c176]Fazle Sadi, Larry T. Pileggi, Franz Franchetti:
Algorithm and hardware co-optimized solution for large SpMV problems. HPEC 2017: 1-7 - [c175]Marko Jereminov, Amritanshu Pandey, Hyun Ah Song, Bryan Hooi, Christos Faloutsos, Larry T. Pileggi:
Linear load model for robust power system analysis. ISGT Europe 2017: 1-6 - [c174]Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi:
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED 2017: 93-98 - [c173]Mehmet Meric Isgenc, Samuel Pagliarini, Renzhi Liu, Larry T. Pileggi:
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. ISQED 2017: 180-185 - [c172]Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi:
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. NANOARCH 2017: 147-152 - [c171]Hyun Ah Song, Bryan Hooi, Marko Jereminov, Amritanshu Pandey, Larry T. Pileggi, Christos Faloutsos:
PowerCast: Mining and Forecasting Power Grid Sequences. ECML/PKDD (2) 2017: 606-621 - [i5]Amritanshu Pandey, Marko Jereminov, Martin R. Wagner, Gabriela Hug, Larry T. Pileggi:
Robust Convergence of Power Flow using Tx Stepping Method with Equivalent Circuit Formulation. CoRR abs/1711.01471 (2017) - [i4]Amritanshu Pandey, Marko Jereminov, Gabriela Hug, Larry T. Pileggi:
Improving Power Flow Robustness via Circuit Simulation Methods. CoRR abs/1711.01624 (2017) - [i3]Amritanshu Pandey, Marko Jereminov, Xin Li, Gabriela Hug, Larry T. Pileggi:
Aggregated Load and Generation Equivalent Circuit Models with Semi-Empirical Data Fitting. CoRR abs/1711.06907 (2017) - 2016
- [j51]Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. Integr. 52: 185-194 (2016) - [c170]Fa Wang, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi:
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. ASP-DAC 2016: 545-550 - [c169]Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi:
Extended statistical element selection: a calibration method for high resolution in analog/RF designs. DAC 2016: 104:1-104:6 - [c168]Fazle Sadi, Larry T. Pileggi, Franz Franchetti:
3D DRAM based application specific hardware accelerator for SpMV. HPEC 2016: 1 - [c167]Rongye Shi, Thomas C. Jackson, Brian Swenson, Soummya Kar, Lawrence T. Pileggi:
On the design of phase locked loop oscillatory neural networks: Mitigation of transmission delay effects. IJCNN 2016: 2039-2046 - [c166]Amritanshu Pandey, Marko Jereminov, Xin Li, Gabriela Hug, Larry T. Pileggi:
Unified power system analyses and models using equivalent circuit formulation. ISGT 2016: 1-5 - [c165]Marko Jereminov, Amritanshu Pandey, David M. Bromberg, Xin Li, Gabriela Hug, Larry T. Pileggi:
Steady-state analysis of power system harmonics using equivalent split-circuit models. ISGT Europe 2016: 1-6 - [c164]L. Richard Carley, Gurkan Colak, Louis Chomas, Larry T. Pileggi, Kenneth Mai:
Technologies for secure RFID authentication of medicinal pills and capsules. RFID-TA 2016: 10-15 - 2015
- [j50]Mohamed M. Sabry, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeffrey Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor L. Markov, Kunle Olukotun, Larry T. Pileggi, Eric Pop, Jan M. Rabaey, Christopher Ré, H.-S. Philip Wong, Subhasish Mitra:
Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. Computer 48(12): 24-33 (2015) - [j49]Vehbi Calayir, Larry T. Pileggi:
Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 162-172 (2015) - [j48]Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi:
Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 230-241 (2015) - [j47]Renzhi Liu, Larry T. Pileggi:
Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 651-655 (2015) - [c163]Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi:
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ASP-DAC 2015: 441-446 - [c162]Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
A synthesis methodology for application-specific logic-in-memory designs. DAC 2015: 196:1-196:6 - [c161]Vehbi Calayir, Mohamed Darwish, Jeffrey A. Weldon, Larry T. Pileggi:
Analog neuromorphic computing enabled by multi-gate programmable resistive devices. DATE 2015: 928-931 - [c160]Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi:
An RRAM-based Oscillatory Neural Network. LASCAS 2015: 1-4 - [c159]Qi Guo, Tze Meng Low, Nikolaos Alachiotis, Berkin Akin, Larry T. Pileggi, James C. Hoe, Franz Franchetti:
Enabling portable energy efficiency with memory accelerated library. MICRO 2015: 750-761 - 2014
- [j46]Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI. IEEE J. Solid State Circuits 49(12): 2891-2901 (2014) - [j45]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman:
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - [c158]Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi:
Toward efficient programming of reconfigurable radio frequency (RF) receivers. ASP-DAC 2014: 256-261 - [c157]Renzhi Liu, Larry T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with >80 dB harmonic rejection ratio. CICC 2014: 1-4 - [c156]Kaushik Vaidyanathan, Bishnu Prasad Das, Larry T. Pileggi:
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack. DAC 2014: 156:1-156:6 - [c155]Minhee Jun, Rohit Negi, Ying-Chih Wang, Tamal Mukherjee, Xin Li, Jun Tao, Larry T. Pileggi:
Joint invariant estimation of RF impairments for reconfigurable Radio Frequency(RF) front-end. GLOBECOM Workshops 2014: 954-959 - [c154]Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - [c153]Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
Efficient and secure intellectual property (IP) design with split fabrication. HOST 2014: 13-18 - [c152]Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory. HPEC 2014: 1-6 - [c151]Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi:
Sub-20 nm design technology co-optimization for standard cell logic. ICCAD 2014: 124-131 - [c150]Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI. ISSCC 2014: 380-381 - [c149]Minhee Jun, Rohit Negi, Jun Tao, Ying-Chih Wang, Shihui Yin, Tamal Mukherjee, Xin Li, Lawrence T. Pileggi:
Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. MILCOM 2014: 1459-1465 - 2013
- [j44]Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry T. Pileggi:
Formal verification of phase-locked loops using reachability analysis and continuization. Commun. ACM 56(10): 97-104 (2013) - [j43]Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j42]Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j41]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [j40]Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry T. Pileggi, Franz Franchetti:
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation. J. Signal Process. Syst. 71(3): 297-312 (2013) - [c148]Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC 2013: 1-7 - [c147]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman:
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - [c146]Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti:
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. HPEC 2013: 1-6 - [c145]Vehbi Calayir, Tom Jackson, Augusto Tazzoli, Gianluca Piazza, Larry T. Pileggi:
Neurocomputing and associative memories based on ovenized aluminum nitride resonators. IJCNN 2013: 1-8 - [c144]Vehbi Calayir, Larry T. Pileggi:
Fully-digital oscillatory associative memories enabled by non-volatile logic. IJCNN 2013: 1-6 - [c143]Vehbi Calayir, Larry T. Pileggi:
All-magnetic analog associative memory. NEWCAS 2013: 1-4 - 2012
- [c142]Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry T. Pileggi, Franz Franchetti:
Design Automation Framework for Application-Specific Logic-in-Memory Blocks. ASAP 2012: 125-132 - [c141]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC 2012: 1-4 - [c140]Fa Wang, Gokce Keskin, Andrew Phelps, Jonathan Rotner, Xin Li, Gary K. Fedder, Tamal Mukherjee, Lawrence T. Pileggi:
Statistical design and optimization for adaptive post-silicon tuning of MEMS filters. DAC 2012: 176-181 - [c139]Daniel Morris, David M. Bromberg, Jian-Gang Jimmy Zhu, Larry T. Pileggi:
mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices. DAC 2012: 486-491 - [c138]Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry T. Pileggi, Franz Franchetti:
Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory. ICASSP 2012: 1557-1560 - [c137]Qiuling Zhu, Larry T. Pileggi, Franz Franchetti:
A Smart Memory Accelerated Computed Tomography Parallel Backprojection. VLSI-SoC (Selected Papers) 2012: 21-44 - [c136]Qiuling Zhu, Larry T. Pileggi, Franz Franchetti:
Cost-effective smart memory implementation for parallel backprojection in computed tomography. VLSI-SoC 2012: 111-116 - 2011
- [j39]Gokce Keskin, Jonathan E. Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi:
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs. IEEE J. Solid State Circuits 46(8): 1904-1918 (2011) - [c135]Soner Yaldiz, Vehbi Calayir, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, José A. Tierno:
Indirect phase noise sensing for self-healing voltage controlled oscillators. CICC 2011: 1-4 - [c134]Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, SangBum Kim, Jonathan E. Proesel, Chung Lam:
Post-silicon calibration of analog CMOS using phase-change memory cells. ESSCIRC 2011: 423-426 - [c133]Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi:
Formal verification of phase-locked loops using reachability analysis and continuization. ICCAD 2011: 659-666 - 2010
- [j38]Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler:
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 509-527 (2010) - [c132]Gokce Keskin, Jonathan E. Proesel, Larry T. Pileggi:
Statistical modeling and post manufacturing configuration for scaled analog CMOS. CICC 2010: 1-4 - [c131]Jonathan E. Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi:
An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection. CICC 2010: 1-4 - [c130]Alyssa Bonnoit, Lawrence T. Pileggi:
Reducing variability in chip-multiprocessors with adaptive body biasing. ISLPED 2010: 73-78
2000 – 2009
- 2009
- [j37]Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd:
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 623-637 (2009) - [c129]Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi:
Creating an affordable 22nm node using design-lithography co-optimization. DAC 2009: 95-96 - [c128]Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi:
SRAM parametric failure analysis. DAC 2009: 496-501 - [c127]Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi:
Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. ISLPED 2009: 207-212 - [c126]Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi:
Efficient statistical analysis of read timing failures in SRAM circuits. ISQED 2009: 617-621 - 2008
- [j36]Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard:
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96(2): 343-365 (2008) - [j35]Xin Li, Yaping Zhan, Lawrence T. Pileggi:
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 831-843 (2008) - [j34]Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1041-1054 (2008) - [c125]Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai, Jonathan E. Proesel:
Mismatch analysis and statistical design at 65 nm and below. CICC 2008: 9-12 - [c124]Jonathan E. Proesel, Lawrence T. Pileggi:
A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS. CICC 2008: 153-156 - [c123]Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi:
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC 2008: 415-418 - [c122]Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi:
Automated Testability Enhancements for Logic Brick Libraries. DATE 2008: 480-485 - 2007
- [j33]Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi:
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 2-15 (2007) - [j32]Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi:
Asymptotic Probability Extraction for Nonnormal Performance Distributions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 16-37 (2007) - [c121]Brian Taylor, Larry T. Pileggi:
Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. DAC 2007: 344-349 - [c120]Xin Li, Lawrence T. Pileggi:
Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits. DAC 2007: 928-933 - [c119]Jian Wang, Xin Li, Lawrence T. Pileggi:
Parameterized Macromodeling for Analog System-Level Design Exploration. DAC 2007: 940-943 - [c118]Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi:
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007: 450-457 - [i2]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif:
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. CoRR abs/0710.4654 (2007) - [i1]Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. CoRR abs/0710.4719 (2007) - 2006
- [j31]Xin Li, Jiayong Le, Lawrence T. Pileggi:
Statistical Performance Modeling and Optimization. Found. Trends Electron. Des. Autom. 1(4) (2006) - [j30]Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra:
IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1763-1776 (2006) - [c117]Gökçe Keskin, Xin Li, Lawrence T. Pileggi:
Active On-Die Suppression of Power Supply Noise. CICC 2006: 813-816 - [c116]Xin Li, Jiayong Le, Lawrence T. Pileggi:
Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. DAC 2006: 103-108 - [c115]Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi:
Architecture-aware FPGA placement using metric embedding. DAC 2006: 460-465 - [c114]Kim Yaw Tong, Lawrence T. Pileggi:
Design Methodology of Regular Logic Bricks for Robust Integrated Circuits. ICCD 2006: 162-167 - 2005
- [j29]Peng Li, Lawrence T. Pileggi:
Compact reduced-order modeling of weakly nonlinear analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 184-203 (2005) - [c113]Rohan Batra, Peng Li, Lawrence T. Pileggi, Wanju Chiang:
A behavioral level approach for nonlinear dynamic modeling of voltage-controlled oscillators. CICC 2005: 717-720 - [c112]Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma:
Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC 2005: 77-82 - [c111]V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks. DAC 2005: 353-358 - [c110]Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi:
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. DAC 2005: 632-637 - [c109]Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. DATE 2005: 164-169 - [c108]Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif:
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE 2005: 958-963 - [c107]Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang:
Performance-centering optimization for system-level analog design exploration. ICCAD 2005: 422-429 - [c106]Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas:
Projection-based performance modeling for inter/intra-die variations. ICCAD 2005: 721-727 - [c105]Xin Li, Peng Li, Lawrence T. Pileggi:
Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. ICCAD 2005: 806-812 - [c104]Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi:
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD 2005: 844-851 - [c103]Peng Li, Yangdong Deng, Lawrence T. Pileggi:
Temperature-Dependent Optimization of Cache Leakage Power Dissipation. ICCD 2005: 7-12 - 2004
- [j28]Yang Xu, Cameron Boone, Lawrence T. Pileggi:
Metal-mask configurable RF front-end circuits. IEEE J. Solid State Circuits 39(8): 1347-1351 (2004) - [j27]Michael W. Beattie, Lawrence T. Pileggi:
Parasitics extraction with multipole refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 288-292 (2004) - [c102]Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd:
ORACLE: optimization with recourse of analog circuits including layout extraction. DAC 2004: 151-154 - [c101]V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi:
Routing architecture exploration for regular fabrics. DAC 2004: 204-207 - [c100]Jiayong Le, Xin Li, Lawrence T. Pileggi:
STAC: statistical timing analysis with correlation. DAC 2004: 343-348 - [c99]Satrajit Gupta, Lawrence T. Pileggi:
CHIME: coupled hierarchical inductance model evaluation. DAC 2004: 800-805 - [c98]Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi:
A frequency relaxation approach for analog/RF system-level simulation. DAC 2004: 842-847 - [c97]Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi:
Exploring Logic Block Granularity for Regular Fabrics. DATE 2004: 468-473 - [c96]Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi:
An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE 2004: 1138-1143 - [c95]Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi:
Asymptotic probability extraction for non-normal distributions of circuit performance. ICCAD 2004: 2-9 - [c94]Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi:
A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD 2004: 275-282 - [c93]Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra:
Efficient full-chip thermal modeling and analysis. ICCAD 2004: 319-326 - [c92]Peng Li, Lawrence T. Pileggi:
Efficient harmonic balance simulation using multi-level frequency decomposition. ICCAD 2004: 677-682 - [c91]Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi:
Robust analog/RF circuit design with projection-based posynomial modeling. ICCAD 2004: 855-862 - [c90]Radu Marculescu, Diana Marculescu, Larry T. Pileggi:
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. ICCD 2004: 168-173 - 2003
- [j26]Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Des. Test Comput. 20(3): 24-31 (2003) - [j25]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Global and local congestion optimization in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 498-505 (2003) - [j24]Peng Li, Lawrence T. Pileggi:
Efficient per-nonlinearity distortion analysis for analog and RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1297-1309 (2003) - [c89]Xin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi:
A frequency separation macromodel for system-level simulation of RF circuits. ASP-DAC 2003: 891-896 - [c88]Peng Li, Lawrence T. Pileggi:
Nonlinear distortion analysis via linear-centric models. ASP-DAC 2003: 897-903 - [c87]Kim Yaw Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit:
Regular logic fabrics for a via patterned gate array (VPGA). CICC 2003: 53-56 - [c86]Hui Zheng, Byron Krauter, Lawrence T. Pileggi:
On-package decoupling optimization with package macromodels. CICC 2003: 723-726 - [c85]Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi:
Fast, cheap and under control: the next implementation fabric. DAC 2003: 354-355 - [c84]Peng Li, Lawrence T. Pileggi:
NORM: compact model order reduction of weakly nonlinear systems. DAC 2003: 472-477 - [c83]Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi:
Analog and RF circuit macromodels for system-level analysis. DAC 2003: 478-483 - [c82]Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, Kim Yaw Tong:
Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787 - [c81]Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi:
Noise Macromodel for Radio Frequency Integrated Circuits. DATE 2003: 10150-10155 - [c80]Aneesh Koorapaty, Vikas Chandra, Kim Yaw Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit:
Heterogeneous Programmable Logic Block Architectures. DATE 2003: 11118-11119 - [c79]Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit:
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL 2003: 426-436 - [c78]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI 2003: 7-10 - [c77]Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiaodong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi:
A fast simulation approach for inductive effects of VLSI interconnects. ACM Great Lakes Symposium on VLSI 2003: 108-111 - [c76]Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi:
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. ICCAD 2003: 454-462 - [c75]Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan:
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD 2003: 491-496 - [c74]Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi:
An architectural exploration of via patterned gate arrays. ISPD 2003: 184-189 - [c73]E. Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi:
Power Comparison of Throughput Optimized IC Busses. ISVLSI 2003: 35-44 - 2002
- [j23]Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje:
An analysis of the wire-load model uncertainty problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 23-31 (2002) - [j22]Emrah Acar, Florentin Dartu, Lawrence T. Pileggi:
TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 605-616 (2002) - [j21]Michael W. Beattie, Lawrence T. Pileggi:
On-chip induction modeling: basics and advanced methods. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 712-729 (2002) - [j20]Ravishankar Arunachalam, Ronald DeShawn Blanton, Lawrence T. Pileggi:
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. VLSI Design 15(3): 605-618 (2002) - [c72]Hui Zheng, Lawrence T. Pileggi:
Modeling and analysis of regular symmetrically structured power/ground distribution networks. DAC 2002: 395-398 - [c71]Tao Lin, Michael W. Beattie, Lawrence T. Pileggi:
On the efficacy of simplified 2D on-chip inductance models. DAC 2002: 757-762 - [c70]Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi:
A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE 2002: 568-575 - [c69]Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter:
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE 2002: 628-633 - [c68]Peng Li, Lawrence T. Pileggi:
A Linear-Centric Modeling Approach to Harmonic Balance Analysis. DATE 2002: 634-639 - [c67]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Congestion-Aware Logic Synthesis. DATE 2002: 664-671 - [c66]Tao Lin, Michael W. Beattie, Lawrence T. Pileggi:
On-Chip Inductance Models: 3D or Not 3D? DATE 2002: 1112 - [c65]Aneesh Koorapaty, Lawrence T. Pileggi:
Modular, Fabric-Specific Synthesis for Programmable Architectures. FPL 2002: 132-141 - [c64]Tao Lin, Lawrence T. Pileggi:
Throughput-driven IC communication fabric synthesis. ICCAD 2002: 274-279 - [c63]Hui Zheng, Lawrence T. Pileggi:
Robust and passive model order reduction for circuits containing susceptance elements. ICCAD 2002: 761-766 - [c62]Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Understanding and addressing the impact of wiring congestion during technology mapping. ISPD 2002: 131-136 - [c61]Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi:
Time-Domain Simulation of Variational Interconnect Models. ISQED 2002: 419-424 - [e1]Lawrence T. Pileggi, Andreas Kuehlmann:
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002. ACM / IEEE Computer Society 2002, ISBN 0-7803-7607-2 [contents] - 2001
- [j19]Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli:
Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE 89(3): 341-365 (2001) - [j18]Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi:
Equipotential shells for efficient inductance extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 70-79 (2001) - [c60]Michael W. Beattie, Lawrence T. Pileggi:
Inductance 101: Modeling and Extraction. DAC 2001: 323-328 - [c59]Michael W. Beattie, Lawrence T. Pileggi:
Modeling Magnetic Coupling for On-Chip Interconnect. DAC 2001: 335-340 - [c58]Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi:
Min/max On-Chip Inductance Models and Delay Metrics. DAC 2001: 341-346 - [c57]Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi:
False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731 - [c56]Michael W. Beattie, Lawrence T. Pileggi:
Efficient inductance extraction via windowing. DATE 2001: 430-436 - [c55]Tao Lin, Lawrence T. Pileggi:
RC(L) interconnect sizing with second order considerations via posynomial programming. ISPD 2001: 16-21 - [c54]Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje:
Overcoming wireload model uncertainty during physical design. ISPD 2001: 182-189 - [c53]Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu:
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED 2001: 431-436 - 2000
- [c52]Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas:
Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171 - [c51]Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer:
Design closure (panel session): hope or hype? DAC 2000: 176-177 - [c50]Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi:
TACO: timing analysis with coupling. DAC 2000: 266-269 - [c49]Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi:
Hierarchical Interconnect Circuit Models. ICCAD 2000: 215-221
1990 – 1999
- 1999
- [j17]Mustafa Celik, Lawrence T. Pileggi:
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 293-300 (1999) - [j16]Michael W. Beattie, Lawrence T. Pileggi:
Error bounds for capacitance extraction via window techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 311-321 (1999) - [c48]Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas:
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC 1999: 201-206 - [c47]Michael W. Beattie, Lawrence T. Pileggi:
IC Analyses Including Extracted Inductance Models. DAC 1999: 915-920 - [c46]Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63 - [c45]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
Practical considerations for passive reduction of RLC circuits. ICCAD 1999: 214-220 - [c44]Michael W. Beattie, Lawrence T. Pileggi:
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. ICCAD 1999: 437-444 - 1998
- [j15]Rony Kay, Lawrence T. Pileggi:
EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 40-49 (1998) - [j14]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 645-654 (1998) - [j13]Rohini Gupta, John Willis, Lawrence T. Pileggi:
Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 457-463 (1998) - [c43]Zhijiang He, Lawrence T. Pileggi:
A simple algorithm for calculating frequency-dependent inductance bounds. CICC 1998: 199-202 - [c42]Rony Kay, Lawrence T. Pileggi:
PRIMO: Probability Interpretation of Moments for Delay Calculation. DAC 1998: 463-468 - [c41]Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas:
ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. DAC 1998: 469-472 - [c40]Florentin Dartu, Lawrence T. Pileggi:
TETA: Transistor-Level Engine for Timing Analysis. DAC 1998: 595-598 - [c39]Tao Lin, Emrah Acar, Lawrence T. Pileggi:
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. ICCAD 1998: 19-25 - [c38]Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi:
Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219 - [c37]Lawrence T. Pileggi:
Timing metrics for physical design of deep submicron technologies. ISPD 1998: 28-33 - 1997
- [j12]Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
Transmission line synthesis via constrained multivariable optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 6-19 (1997) - [j11]Rohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi:
The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 95-104 (1997) - [j10]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2): 210-215 (1997) - [j9]Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 867-881 (1997) - [c36]Florentin Dartu, Lawrence T. Pileggi:
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51 - [c35]Michael W. Beattie, Lawrence T. Pileggi:
Bounds for BEM Capacitance Extraction. DAC 1997: 133-136 - [c34]Zhijiang He, Mustafa Celik, Lawrence T. Pileggi:
SPIE: Sparse Partial Inductance Extraction. DAC 1997: 137-140 - [c33]Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi:
PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD 1997: 58-65 - [c32]Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar:
A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273 - [c31]Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi:
Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223 - [c30]Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi:
CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229 - [c29]Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi:
EWA: exact wiring-sizing algorithm. ISPD 1997: 178-185 - 1996
- [j8]Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi:
Domain characterization of transmission line models and analyses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 184-193 (1996) - [j7]Florentin Dartu, Noel Menezes, Lawrence T. Pileggi:
Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 544-553 (1996) - [j6]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 691-701 (1996) - [c28]Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi:
A Sparse Image Method for BEM Capacitance Extraction. DAC 1996: 357-362 - [c27]Florentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi:
RC-Interconnect Macromodels for Timing Simulation. DAC 1996: 544-547 - [c26]Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi:
An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC 1996: 611-616 - [c25]Rohini Gupta, Byron Krauter, Lawrence T. Pileggi:
On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. VLSI Design 1996: 150-155 - 1995
- [c24]Byron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi:
Transmission Line Synthesis. DAC 1995: 358-363 - [c23]Rohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi:
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. DAC 1995: 364-369 - [c22]Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi:
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695 - [c21]Byron Krauter, Lawrence T. Pileggi:
Generating sparse partial inductance matrices with guaranteed stability. ICCAD 1995: 45-52 - [c20]Rohini Gupta, Lawrence T. Pileggi:
Constrained multivariable optimization of transmission lines with general topologies. ICCAD 1995: 130-137 - [c19]Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD 1995: 144-151 - [c18]Lawrence T. Pileggi:
Coping with RC(L) interconnect design headaches. ICCAD 1995: 246-253 - 1994
- [j5]Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage:
Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 729-736 (1994) - [j4]Curtis L. Ratzlaff, Lawrence T. Pillage:
RICE: rapid interconnect circuit evaluation using AWE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 763-776 (1994) - [j3]Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage:
Time-domain macromodels for VLSI interconnect analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1257-1270 (1994) - [j2]Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage:
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1526-1535 (1994) - [c17]Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage:
A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580 - [c16]Rohini Gupta, Lawrence T. Pillage:
OTTER: Optimal Termination of Transmission Lines Excluding Radiation. DAC 1994: 640-645 - [c15]Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337 - [c14]Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425 - [c13]Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage:
Domain Characterization of Transmission Line Models for Efficient Simulation. ICCD 1994: 558-562 - 1993
- [c12]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage:
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170 - [c11]Dah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh:
Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. DAC 1993: 367-372 - [c10]S. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, Thomas L. Savarino, Dean P. Neikirk, Lawrence T. Pillage:
An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. ICCAD 1993: 58-65 - 1992
- [c9]Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage:
On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. DAC 1992: 207-212 - [c8]Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage:
AWE macromodels of VLSI interconnect for circuit simulation. ICCAD 1992: 64-70 - [c7]Ronn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage:
ETA: electrical-level timing analysis. ICCAD 1992: 258-262 - 1991
- [c6]Curtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage:
RICE: Rapid Interconnect Circuit Evaluator. DAC 1991: 555-560 - [c5]Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage:
Evaluating RC-Interconnect Using Moment-Matching Approximations. ICCAD 1991: 74-77 - 1990
- [j1]Lawrence T. Pillage, Ronald A. Rohrer:
Asymptotic waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 352-366 (1990) - [c4]Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage:
DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. ICCAD 1990: 546-549
1980 – 1989
- 1989
- [c3]Xueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer:
Efficient Final Placement Based on Nets-as-Points. DAC 1989: 578-581 - [c2]Lawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer:
AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. DAC 1989: 634-637 - 1988
- [c1]Lawrence T. Pillage, Ronald A. Rohrer:
A Quadratic Metric with a Simple Solution Scheme for Initial Placement. DAC 1988: 324-329
Coauthor Index
[i3] [c170] [c166] [c165] [c163] [j45] [c158] [c155] [c149] [j44] [j43] [j42] [c147] [c140] [c135] [c133] [j37] [c128] [c126] [j36] [j35] [j34] [c125] [c123] [j33] [j32] [c120] [c119] [c118] [i2] [j31] [c117] [c116] [c115] [c112] [c110] [c108] [c107] [c106] [c105] [c104] [c100] [c98] [c95] [c91] [c89] [c83] [c81] [c76]
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