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ORCID23rd ISQED 2022: Santa Clara, CA, USA
- 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022. IEEE 2022, ISBN 978-1-6654-9466-3
- Xiangdong Wei, Xinfei Guo:
Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs. 1 - Simon Thomann
, Hong L. G. Nguyen, Hussam Amrouch:
HW/SW Codesign for Approximate In-Memory Computing. 1-6 - Arman Roohi, Shaahin Angizi, Pooriya Navaeilavasani, MohammadReza Taheri:
ReFACE: Efficient Design Methodology for Acceleration of Digital Filter Implementations. 1-6 - Andres Martinez-Sanchez, Deva K. Borah, Wenjie Che:
A Lightweight Neighbor-Averaging Technique for Reducing Systematic Variations in Physically Unclonable Functions. 1-6 - Wei Wei, Sahidul Islam, Jishnu Banerjee, Shanglin Zhou, Chen Pan, Caiwen Ding, Mimi Xie:
An Intermittent OTA Approach to Update the DL Weights on Energy Harvesting Devices. 1-6 - Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang:
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. 1-6 - Venkateswar Kowkutla, Siva Kothamasu, Kazunobu Shin, Chunhua Hu:
Pushing Low Power Limits on Multi-Core High Performance SoC. 1-4 - Behnam Ghavami, Seyd Movi, Zhenman Fang, Lesley Shannon:
Stealthy Attack on Algorithmic-Protected DNNs via Smart Bit Flipping. 1-7 - Xinpei Zhang, Yi Ding, Mingfei Yu, Shin-ichi O'Uchi, Masahiro Fujita:
Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. 1-6 - Jianfeng Song, Dana Porter, Jiang Hu, Thomas H. Marek:
Double Deep Q-Learning Based Irrigation and Chemigation Control. 1-6 - Ourania Spantidi, Iraklis Anagnostopoulos:
How much is too much error? Analyzing the impact of approximate multipliers on DNNs. 1-6 - April L. Reed, Xiaokun Yang, Shi Sha:
Lightweight Neural Network Architectures for Resource-Limited Devices. 1-7 - Ruben Purdy, R. D. Shawn Blanton:
Large-Scale Logic-Locking Attacks via Simulation. 1-6 - Konstantinos Balaskas, Georgios Zervakis, Kostas Siozios, Mehdi B. Tahoori, Jörg Henkel:
Approximate Decision Trees For Machine Learning Classification on Tiny Printed Circuits. 1-6 - Hafiz Md. Hasan Babu, Khandaker Mohammad Mohi Uddin, Rownak Borhan Himel, Nitish Biswas:
Quantum Technology for Comparator Circuit. 1 - Rajat Butola, Yiming Li, Sekhar Reddy Kola:
Machine Learning Approach to Characteristic Fluctuation of Bulk FinFETs Induced by Random Interface Traps. 1-6 - Zhihui Gao, Minxue Tang, Ang Li, Yiran Chen:
An Audio Frequency Unfolding Framework for Ultra-Low Sampling Rate Sensors. 1-6 - Fabiha Nowshin, Yang Yi:
Memristor-based Deep Spiking Neural Network with a Computing-In-Memory Architecture. 1-6 - Ali Heydarigorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
In-storage Processing of I/O Intensive Applications on Computational Storage Drives. 1-6 - Ya-Shu Yang, Yiming Li:
Model Auto Extraction for Gate-All-Around Silicon Nanowire MOSFETs Using A Decomposition-Based Many-Objective Evolutionary Algorithm. 1-6 - Prosenjit Kumar Ghosh, Prabha Sundaravdivel:
i-lete: An IoT-based physical stress monitoring framework for athletes. 1-6 - Saya Inagaki, Mingyu Yang, Yang Li, Kazuo Sakiyama, Yuko Hara-Azumi:
Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks. 1 - Bijay Raj Paudel, Vasileios Pentsos, Spyros Tragoudas:
On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks. 1-7 - Vivek Raghunathan, Karl Muth, Bapiraju Vinnakota, Prasad Venugopal, Rebecca Schaevitz, Manish Mehta:
SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP). 1-6 - Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, Babita Jajodia:
EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification. 1-7 - Mahdieh Grailoo, Mairo Leier, Samuel Pagliarini:
Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks. 1-6 - Sekhar Reddy Kola, Yiming Li, Chieh-Yang Chen, Min-Hui Chuang:
A Unified Statistical Analysis of Comprehensive Fluctuations of Gate-All-Around Silicon Nanosheet MOSFETs Induced by RDF, ITF, and WKF Simultaneously. 1-6 - Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay:
Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking. 1-6 - Mostafa Abdelrehim, Ahmad Patooghy, Amin Malekmohammadi, Abdel-Hameed A. Badawy:
BIC: Blind Identification Countermeasure for Malicious Thermal Sensor Attacks in Mobile SoCs. 1-6 - Yuan Song, Bi Wu, Tian Yuan, Weiqiang Liu:
A High-Speed CNN Hardware Accelerator with Regular Pruning. 1-5 - Kuei-Huan Chang, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen:
On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network. 1-6 - Melvin Galicia, Farhad Merchant, Rainer Leupers:
A Parallel SystemC Virtual Platform for Neuromorphic Architectures. 1-6 - Amir Ali Pour, David Hély, Vincent Beroulle, Giorgio Di Natale:
Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning. 1 - Zachary Kerman, Chunxiu Yu, Hongyu An:
Beta Oscillation Detector Design for Closed-Loop Deep Brain Stimulation of Parkinson's Disease with Memristive Spiking Neural Networks. 1-6 - Danushka Senarathna, Spyros Tragoudas:
Computation of Soft Error Rates Considering Test Pattern Sequences. 1-6 - Ruihao Li, Aman Arora, Sikan Li, Qinzhe Wu, Lizy K. John:
Hardware-aware 3D Model Workload Selection and Characterization for Graphics and ML Applications. 1-8 - Eduardo Juárez, Raquel Lazcano, Daniel Madroñal, César Sanz:
Energy Consumption and Runtime Performance Optimizations Applied to Hyperspectral Imaging Cancer Detection. 1-8 - Michael Gansen, Jie Lou, Florian Freye, Tobias Gemmeke, Farhad Merchant, Albert Zeyer, Mohammad Zeineldeen, Ralf Schlüter, Xin Fan:
Discrete Steps towards Approximate Computing. 1-6 - Chunxiao Lin, Yibin Liang, Yang Yi:
FPGA-based Reservoir Computing with Optimized Reservoir Node Architecture. 1-6 - Vaibhav Venugopal Rao, Avesta Sasan, Ioannis Savidis:
Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits. 1-7 - Yuxuan Pan, Zhonghua Zhou, André Ivanov:
Routability-driven Global Routing with 3D Congestion Estimation Using a Customized Neural Network. 1-6 - Fatma Ozudogru, Sercan Koca, Seval Kinden, Shawana Tabassum:
Multilayered Triboelectric Energy Harvester as a Smart Floor Mat. 1-4 - Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data Applications. 1-6 - Hongzhi Xu, Binlian Zhang, Chen Pan:
Aperiodic Tasks Scheduling of Energy Harvesting Embedded Systems. 1-6 - Seema G. Aarella, Ajaya Kumar Tripathy, Saraju P. Mohanty, Elias Kougianos:
EasyBand2.0: A Framework with Context-Aware Recommendation Mechanism for Safety-Aware Mobility during Pandemic Outbreaks. 1-6 - Fynn Kappelhoff, Rasmus Rasche, Debdeep Mukhopadhyay, Ulrich Rührmair:
Strong PUF Security Metrics: Response Sensitivity to Small Challenge Perturbations. 1-10 - Baoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng:
Thermal Modeling and Design Exploration for Monolithic 3D ICs. 1-6 - Nafize Ishtiaque Hossain, Shawana Tabassum:
An IoT-enabled Electronic Textile-based Flexible Body Sensor Network for Real-time Health Monitoring in Assisted Living during Pandemic. 1-5 - Dongning Ma, Xue Qin, Xun Jiao:
AxBy-ViT: Reconfigurable Approximate Computation Bypass for Vision Transformers. 1-5 - Pragnesh Patel, Aman Arora, Earl E. Swartzlander Jr., Lizy K. John:
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning. 1-7 - Shaahin Angizi, Arman Roohi:
Integrated Sensing and Computing using Energy-Efficient Magnetic Synapses. 1-4 - Srivatsa Rangachar Srinivasa, Jainaveen Sundaram Priya, Dileep Kurian, Erika Ramirez Lozano, Satish Yada, Saransh Chhabra, Kamakhya Prasad Sahu, Paolo A. Aseron, Ronald Kalim, Anuradha Srinivasan, Tanay Karnik:
Design Methodology for Scalable 2.5D/3D Heterogenous Tiled Chiplet Systems. 1-4 - Shinichi Nishizawa, Toru Nakura:
Density Aware Cell Library Design for Design-Technology Co-Optimization. 1 - Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee:
HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications. 1-5 - Mohammad Eslami, Tara Ghasempouri, Samuel Pagliarini:
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection. 1-6 - Shaoyi Huang, Ning Liu, Yueying Liang, Hongwu Peng, Hongjia Li, Dongkuan Xu, Mimi Xie, Caiwen Ding:
An Automatic and Efficient BERT Pruning for Edge AI Systems. 1-6 - Zhikai Wang, Wenfei Hu, Jingbo Zhou, Wenyuan Zhang, Ruitao Wang, Jian Zhang, Dejing Dou, Zuochang Ye, Yan Wang:
Building Post-layout Performance Model of Analog/RF Circuits by Fine-tuning Technique. 1-6 - Sina Shahhosseini, Tianyi Hu, Dongjoo Seo, Anil Kanduri, Bryan Donyanavard, Amir M. Rahmani, Nikil D. Dutt:
Hybrid Learning for Orchestrating Deep Learning Inference in Multi-user Edge-cloud Networks. 1-6 - Sowmith Nethula, Vivek Bansal, Ghaith Bany Hamad, Otmane Aït Mohamed:
Layout-based Vulnerability Analysis of LEON3 Processor to Single Event Multiple Transients using Satisfiability Modulo Theories. 1-6 - Chen Nie, Zongwu Wang, Qidong Tang, Chenyang Lv, Li Jiang, Zhezhi He:
Cross-layer Designs against Non-ideal Effects in ReRAM-based Processing-in-Memory System. 1-6 - Amir Ali Pour, David Hély, Vincent Beroulle, Giorgio Di Natale:
An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer Learning. 1-6 - Usman Ali, Salman Abdul Khaliq, Omer Khan:
Characterization of mitigation schemes against timing-based side-channel attacks on PCIe hardware. 1-6 - Zahra Kazemi, Amin Norollah, Mahdi Fazeli, David Hély, Vincent Beroulle:
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding. 1 - Tsao-Hsuan Peng, Chih-Chun Hsu, Po-Chun Wang, Rung-Bin Lin:
Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology. 1-6 - Wen Zhang, Wenlu Wang, Mehdi Sookhak, Chen Pan:
Joint-optimization of Node Placement and UAV's Trajectory for Self-sustaining Air-Ground IoT system. 1-6 - Xiaolong Ma, Geng Yuan, Zhengang Li, Yifan Gong, Tianyun Zhang, Wei Niu, Zheng Zhan, Pu Zhao, Ning Liu, Jian Tang, Xue Lin, Bin Ren, Yanzhi Wang:
BLCR: Towards Real-time DNN Execution with Block-based Reweighted Pruning. 1-8 - Zahra Heshmatpour, Lihong Zhang, Howard M. Heys:
Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits. 1-6 - Sandeep Miryala, Md. Adnan Zaman, Sandeep Mittal, Yihui Ren, Grzegorz Deptuch, Gabriella Carini, Sioan Zohar, Shinjae Yoo, Jack Fried, Jin Huang, Srinivas Katkoori:
Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications. 1-6 - Rabin Yu Acharya, Domenic Forte:
Joint Optimization of NCL PUF Using Frequency-based Analysis and Evolutionary Algorithm. 1-6 - Sourav Roy, Tasnuva Farheen, Shahin Tajik, Domenic Forte:
Self-timed Sensors for Detecting Static Optical Side Channel Attacks. 1-6 - Mohammad Mezanur Rahman Monjur, Joseph Heacock, Joshua Calzadillas, Rui Sun, Qiaoyan Yu:
Challenges of Securing Low-Power LoRaWAN Devices Deployed in Advanced Manufacturing. 1 - Hassan Afzali-Kusha, Massoud Pedram:
X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach. 7-12 - Keonjoo Lee, Donghyun Kang, Duseok Kang, Soonhoi Ha:
Analysis of the Effect of Off-chip Memory Access on the Performance of an NPU System. 13-18 - Sandeep Miryala, Gabriella Carini, Grzegorz Deptuch, Jin Huang, Srinivas Katkoori, Piotr Maj, Soumyajit Mandal, Yihui Ren, Md. Adnan Zaman:
Design and Challenges of Edge Computing ASICs on Front-End Electronics. 19-27 - Shi-Tang Liu, Jia-Xian Chen, Yu-Tsung Wu, Chao-Ho Hsieh, Chien-Mo James Li, Norman Chang, Ying-Shiun Li, Wentze Chuang:
Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor. 27-32 - Sam C. Lo, Aaron J. Barker, Stephen R. Whiteley, Eric Mlinar, Jiajun Chen, Dehuang Wu, Kishore Singhal:
Simulation methodology for timing analysis and design optimization in digital superconducting electronics. 33-38 - Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, Franco Fummi:
Functional Level Abstraction and Simulation of Verilog-AMS Piecewise Linear Models. 39-44 - Pingakshya Goswami, Dinesh Bhatia:
Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. 45-50 - Sadia Azam, Nicola Dall'Ora, Enrico Fraccaroli, André Alberts, Renaud Gillon, Franco Fummi:
Investigation on Realistic Stuck-on/off Defects to Complement IEEE P2427 Draft Standard. 51-57 - Jitendra Kumar, Asutosh Srivastava, Masahiro Fujita:
Formal Analysis of Integer Multipliers by building Binary Decision Diagram of Adder Trees. 58-63 - Mohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa:
DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis. 64-70 - Saumil Gogri, Aakash Tyagi, Michael Quinn, Jiang Hu:
Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors. 71-76 - Hosein Mohammadi Makrani, Zhangying He, Setareh Rafatirad, Hossein Sayadi:
Accelerated Machine Learning for On-Device Hardware-Assisted Cybersecurity in Edge Platforms. 77-83 - Mohammad Ebrahimabadi, Bijan Fadaeinia, Amir Moradi, Naghmeh Karimi:
Does Aging Matter? The Curious Case of Fault Sensitivity Analysis. 84-89 - Benjamin Tan:
Challenges and Opportunities for Hardware-Assisted Security Improvements in the Field. 90-95 - Ali Mirzaeian, Zhi Tian, Sai Manoj P. D., Banafsheh S. Latibari, Ioannis Savidis, Houman Homayoun, Avesta Sasan:
Adaptive-Gravity: A Defense Against Adversarial Samples. 96-101 - Marzieh Vaeztourshizi, Massoud Pedram:
An Efficient Error Estimation Technique for Pruning Approximate Data-Flow Graphs in Design Space Exploration. 102-107 - Mihnea Chirila, Paolo D'Alberto, Hsin-Yu Ting, Alexander V. Veidenbaum, Alexandru Nicolau:
A Heterogeneous Solution to the All-pairs Shortest Path Problem using FPGAs. 108-113 - Yousef Safari, Boris Vaisband:
Integrated Power Delivery Methodology for 3D ICs. 114-119 - Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie:
FastMem: A Fast Architecture-aware Memory Layout Design. 120-126 - Mohammad Hajijafari, Mehrnaz Ahmadi, Zhenxin Zhao, Lihong Zhang:
Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control. 127-132
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last updated on 2025-01-10 18:41 CET by the dblp team
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