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ORCIDStefan Wildermann
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- affiliation: Friedrich Alexander University of Erlangen-Nuremberg, Erlangen, Germany
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2020 – today
- 2024
[j22]Jan Spieck
, Stefan Wildermann, Jürgen Teich:
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-43 (2024)- [j21]Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. 17(2): 24:1-24:28 (2024) - [c80]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE 2024: 1-2 - [c79]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS 2024: 79-85 - [c78]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. DIMES@SOSP 2024: 17-24 - [c77]Paul Krüger, Stefan Wildermann, Jürgen Teich:
CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS 2024: 37-43 - [c76]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. FPL 2024: 11-18 - [c75]Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO 2024: 1-5 - [c74]Nils Wilbert, Stefan Wildermann, Jürgen Teich:
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. MEMSYS 2024: 257-269 - [e2]Patrick Meumeu Yomsi, Stefan Wildermann:
Fifth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2024, January 17-19, 2024, Munich, Germany. OASIcs 117, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2024, ISBN 978-3-95977-313-3 [contents] - 2023
- [j20]Jan Spieck, Stefan Wildermann, Jürgen Teich:
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. 28(1): 4:1-4:40 (2023) - [j19]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. 28(6): 98:1-98:20 (2023) - [c73]Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW 2023: 729-749 - [c72]Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20 - [c71]Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich:
Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE 2023: 133-139 - [c70]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL 2023: 189-196 - [c69]Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich:
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC 2023: 7:1-7:16 - [c68]Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich:
Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE 2023: 23-35 - [e1]Georgios I. Goumas, Sven Tomforde, Jürgen Brehm, Stefan Wildermann, Thilo Pionteck:
Architecture of Computing Systems - 36th International Conference, ARCS 2023, Athens, Greece, June 13-15, 2023, Proceedings. Lecture Notes in Computer Science 13949, Springer 2023, ISBN 978-3-031-42784-8 [contents] - 2022
- [j18]Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich:
Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access 10: 33787-33802 (2022) - [j17]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. 64(3): 89-98 (2022) - [j16]Jan Spieck, Stefan Wildermann, Jürgen Teich:
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4289-4300 (2022) - [j15]Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich:
Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 345-366 (2022) - [j14]Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 7:1-7:27 (2022) - [c67]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS 2022: 65-74 - [c66]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. DATE 2022: 250-255 - [c65]Jens Trautmann, Jürgen Teich, Stefan Wildermann:
Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM 2022: 1-9 - [c64]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL 2022: 94-100 - [c63]Tobias Hahn, Stefan Wildermann, Jürgen Teich:
Auto-Tuning of Raw Filters for FPGAs. FPL 2022: 167-175 - [c62]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC 2022: 2:1-2:13 - [c61]Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich:
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS 2022: 329-345 - [i6]Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Raw Filtering of JSON Data on FPGAs. CoRR abs/2205.05464 (2022) - [i5]Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann:
Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR abs/2206.10368 (2022) - 2021
- [j13]Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich:
Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum 21(1): 55-64 (2021) - [c60]Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich:
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC 2021: 242-253 - [c59]Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann:
Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems 2021: 125-149 - [c58]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. DATE 2021: 1552-1557 - [c57]Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
Choice - A Tunable PUF-Design for FPGAs. FPL 2021: 38-44 - [c56]Khalil Esper, Stefan Wildermann, Jürgen Teich:
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC 2021: 1:1-1:12 - [c55]Khalil Esper, Stefan Wildermann, Jürgen Teich:
Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE 2021: 21-31 - [c54]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD 2021: 1-6 - [c53]Jens Schlumberger, Stefan Wildermann, Jürgen Teich:
CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS 2021: 1-5 - [i4]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich:
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR abs/2105.05588 (2021) - 2020
- [c52]Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann:
Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC 2020: 629-636 - [c51]Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. DAC 2020: 1-6 - [c50]Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC 2020: 1-6 - [c49]Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich:
SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT 2020: 639-642 - [c48]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. NG-RES@HiPEAC 2020: 5:1-5:14 - [c47]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST 2020: 102-110 - [i3]Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich:
Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR abs/2004.09453 (2020)
2010 – 2019
- 2019
- [j12]Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Hard real-time application mapping reconfiguration for NoC-based many-core systems. Real Time Syst. 55(2): 433-469 (2019) - [j11]Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich:
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. ACM Trans. Design Autom. Electr. Syst. 24(3): 29:1-29:23 (2019) - [c46]Dirk Gabriel, Walter Stechele, Stefan Wildermann:
Resource-Aware Parameter Tuning for Real-Time Applications. ARCS 2019: 45-55 - [c45]Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich:
ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) 2019: 51-70 - [c44]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. ECRTS 2019: 12:1-12:24 - [c43]Jan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich, Michael Glaß:
Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems. MCSoC 2019: 334-341 - [c42]Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig 2019: 1-8 - [c41]Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jürgen Teich, Jörg Henkel:
Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. RTSS 2019: 220-232 - [i2]Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich:
Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. CoRR abs/1905.13503 (2019) - 2018
- [b2]Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Computer Architecture and Design Methodologies, Springer 2018, ISBN 978-981-10-7355-7, pp. I-XXII, 1-164 - [j10]Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann:
Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum 18(3): 145-156 (2018) - [j9]Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich:
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embed. Syst. Lett. 10(2): 37-40 (2018) - [j8]Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich:
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 297-310 (2018) - [j7]Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich:
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Trans. Embed. Comput. Syst. 17(5): 89:1-89:25 (2018) - [c40]Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß:
Architecture decomposition in system synthesis of heterogeneous many-core systems. DAC 2018: 175:1-175:6 - [c39]Andreas Becher, Stefan Wildermann, Jürgen Teich:
Optimistic regular expression matching on FPGAs for near-data processing. DaMoN 2018: 4:1-4:3 - [c38]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. FPT 2018: 326-329 - [c37]Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Design space exploration of multi-output logic function approximations. ICCAD 2018: 52 - [c36]Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch:
Dynamic resource management for heterogeneous many-cores. ICCAD 2018: 60 - [c35]Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich:
Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS 2018: 841-844 - [c34]Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich:
On the Complexity of Mapping Feasibility in Many-Core Architectures. MCSoC 2018: 176-183 - [c33]Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich:
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig 2018: 1-8 - 2017
- [j6]Birgit Vogel-Heuser, Stefan Wildermann, Jürgen Teich:
Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems. Prod. Eng. 11(6): 687-694 (2017) - [c32]Franz-Josef Streit, Martín Letras, Matthias Schid, Joachim Falk, Stefan Wildermann, Jürgen Teich:
High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. ICDSC 2017: 174-179 - [c31]Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich:
Predictable run-time mapping reconfiguration for real-time applications on many-core systems. RTNS 2017: 148-157 - [c30]Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jürgen Teich, Stefan Wildermann:
Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. SCOPES 2017: 64-67 - [c29]Martín Letras, Joachim Falk, Stefan Wildermann, Jürgen Teich:
Automatic Conversion of Simulink Models to SysteMoC Actor Networks. SCOPES 2017: 81-84 - [c28]Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann:
Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES 2017: 89-92 - [i1]Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich:
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. CoRR abs/1711.05932 (2017) - 2016
- [j5]Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau:
Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. 58(6): 267-280 (2016) - [j4]Gabor Drescher, Christoph Erhardt, Felix C. Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner, Stefan Wildermann:
Providing security on demand using invasive computing. it Inf. Technol. 58(6): 281-295 (2016) - [c27]Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich:
A LUT-Based Approximate Adder. FCCM 2016: 27 - [c26]Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener:
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT 2016: 213-216 - [c25]Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann:
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. MCSoC 2016: 313-320 - [c24]Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich:
ActorX10: an actor library for X10. X10@PLDI 2016: 24-29 - [c23]Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann:
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig 2016: 1-7 - [c22]Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich:
ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig 2016: 1-8 - [c21]Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich:
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. SCOPES 2016: 153-162 - 2015
- [c20]Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich:
Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia 2015: 1-2 - [c19]Stefan Wildermann, Andreas Weichslgartner, Jürgen Teich:
Design Methodology and Run-Time Management for Predictable Many-Core Systems. ISORC Workshops 2015: 103-110 - 2014
- [c18]Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, Jürgen Teich:
DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. CODES+ISSS 2014: 34:1-34:10 - [c17]Stefan Wildermann, Michael Glaß, Jürgen Teich:
Multi-objective distributed run-time resource management for many-cores. DATE 2014: 1-6 - [c16]Stefan Wildermann, Jürgen Teich:
Self-Integration for Virtualization of Embedded Many-Core Systems. SASO Workshops 2014: 170-177 - 2013
- [j3]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. 17(2): 343-375 (2013) - [c15]Stefan Wildermann, Tobias Ziermann, Jürgen Teich:
Game-theoretic analysis of decentralized core allocation schemes on many-core systems. DATE 2013: 1498-1503 - 2012
- [b1]Stefan Wildermann:
Systematic design of self-adaptive embedded systems with applications in image processing. University of Erlangen-Nuremberg, 2012, pp. 1-215 - [j2]Tobias Ziermann, Stefan Wildermann, Nina Mühleis, Jürgen Teich:
Distributed self-organizing bandwidth allocation for priority-based bus communication. Concurr. Comput. Pract. Exp. 24(16): 1903-1917 (2012) - [j1]Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich:
Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2012: 608312:1-608312:12 (2012) - 2011
- [c14]Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich:
Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS 2011: 129-138 - [c13]Stefan Wildermann, Jürgen Teich, Daniel Ziener:
Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL 2011: 429-434 - [c12]Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic:
Operational mode exploration for reconfigurable systems with multiple applications. FPT 2011: 1-8 - [c11]Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich:
Dynamic decentralized mapping of tree-structured applications on NoC architectures. NOCS 2011: 201-208 - [p1]Tobias Ziermann, Stefan Wildermann, Jürgen Teich:
OrganicBus: Organic Self-organising Bus-Based Communication Systems. Organic Computing 2011: 489-501 - 2010
- [c10]Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic:
Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. ATC 2010: 1-16 - [c9]Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch:
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL 2010: 234-239 - [c8]Tobias Ziermann, Nina Mühleis, Stefan Wildermann, Jürgen Teich:
A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. ISORC Workshops 2010: 11-20 - [c7]Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich:
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. ReConFig 2010: 91-96
2000 – 2009
- 2009
- [c6]Tobias Ziermann, Stefan Wildermann, Jürgen Teich:
CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE 2009: 1088-1093 - [c5]Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich:
Self-organizing multi-cue fusion for FPGA-based embedded imaging. FPL 2009: 132-137 - [c4]Stefan Wildermann, Tobias Ziermann, Jürgen Teich:
Self-organizing Bandwidth Sharing in Priority-Based Medium Access. SASO 2009: 144-153 - 2008
- [c3]Stefan Wildermann, Jürgen Teich:
A Sequential Learning Resource Allocation Network for Image Processing Applications. HIS 2008: 132-137 - [c2]Stefan Wildermann, Jürgen Teich:
3D Person Tracking with a Color-Based Particle Filter. RobVis 2008: 327-340 - [c1]Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich:
Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping 2008: 142-148
Coauthor Index
[j22] [j21] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [j20] [j19] [c73] [c72] [c71] [c70] [c69] [c68] [j18] [j17] [j16] [j15] [j14] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [i6] [i5] [j13] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [i4] [c52] [c51] [c50] [c49] [c48] [c47] [i3] [j12] [j11] [c45] [c44] [c43] [c42] [c41] [i2] [b2] [j10] [j9] [j8] [j7] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [j6] [c32] [c31] [c30] [c29] [c28] [i1] [j5] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [j3] [c15] [j2] [j1] [c14] [c13] [c12] [c11] [p1] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
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Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-13 02:07 CET by the dblp team
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