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2010 – 2019
- 2011
[j77]Kan Wang
, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong:
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011)- [c181]Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - 2010
- [j76]Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng:
Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1196-1203 (2010) - [j75]Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong:
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19(7): 1483-1495 (2010) - [j74]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. 15(3): 27:1-27:21 (2010) - [j73]Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong:
ECP- and CMP-Aware Detailed Routing Algorithm for DFM. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 153-157 (2010) - [j72]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1639-1648 (2010) - [c180]Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang:
Simultaneous slack budgeting and retiming for synchronous circuits optimization. ASP-DAC 2010: 49-54 - [c179]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ASP-DAC 2010: 769-774
2000 – 2009
- 2009
- [j71]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
A single layer zero skew clock routing in X architecture. Sci. China Ser. F Inf. Sci. 52(8): 1466-1475 (2009) - [j70]Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng:
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1476-1484 (2009) - [j69]Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong:
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2979-2989 (2009) - [j68]Haixia Yan, Qiang Zhou, Xianlong Hong:
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. Integr. 42(2): 175-180 (2009) - [j67]Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong:
An MTCMOS technology for low-power physical design. Integr. 42(3): 340-345 (2009) - [j66]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 207-216 (2009) - [c178]Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. ASP-DAC 2009: 161-166 - [c177]Xin Li, Yuchun Ma, Xianlong Hong:
A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC 2009: 347-352 - [c176]Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
Fast placement for large-scale hierarchical FPGAs. CAD/Graphics 2009: 190-194 - [c175]Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles:
An efficient decoupling capacitance optimization using piecewise polynomial models. DATE 2009: 1190-1195 - [c174]Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang:
Multi-objective Floorplanning Based on Fuzzy Logic. FSKD (4) 2009: 331-335 - [c173]Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto:
Buffer Planning for 3D ICs. ISCAS 2009: 1735-1738 - [c172]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Diffusion-driven congestion reduction for substrate topological routing. ISPD 2009: 175-180 - [c171]Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong:
Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286 - [c170]Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong:
Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510 - [c169]Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 - [c168]Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng:
Efficient power network analysis with complete inductive modeling. ISQED 2009: 770-775 - [c167]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
Modern Floorplanning with Boundary Clustering Constraint. ISVLSI 2009: 79-84 - [c166]Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto:
Integrated interlayer via planning and pin assignment for 3D ICs. SLIP 2009: 99-104 - 2008
- [j65]Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang:
Application of optical proximity correction technology. Sci. China Ser. F Inf. Sci. 51(2): 213-224 (2008) - [j64]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Low Power Gated Clock Tree Driven Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 595-603 (2008) - [j63]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2084-2090 (2008) - [j62]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3443-3450 (2008) - [j61]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3783-3792 (2008) - [j60]Hailong Yao, Subarna Sinha, Jingyu Xu, Charles C. Chiang, Yici Cai, Xianlong Hong:
Efficient range pattern matching algorithm for process-hotspot detection. IET Circuits Devices Syst. 2(1): 2-15 (2008) - [j59]Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan:
Large scale P/G grid transient simulation using hierarchical relaxed approach. Integr. 41(1): 153-160 (2008) - [j58]Tom Tong Jing, Yu Hu, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integr. 41(3): 413-425 (2008) - [j57]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integr. 41(3): 426-438 (2008) - [j56]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 726-737 (2008) - [j55]Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 1996-2006 (2008) - [j54]Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Random Walk Guided Decap Embedding for Power/Ground Network Optimization. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 36-40 (2008) - [j53]Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 2064-2075 (2008) - [c165]Changdao Dong, Qiang Zhou, Yici Cai, Xianlong Hong:
Wire density driven top-down global placement for CMP variation control. APCCAS 2008: 1676-1679 - [c164]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c163]Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375 - [c162]Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Heuristic power/ground network and floorplan co-design method. ASP-DAC 2008: 617-622 - [c161]Shuai Li, Jin Shi, Yici Cai, Xianlong Hong:
Vertical via design techniques for multi-layered P/G networks. ASP-DAC 2008: 623-628 - [c160]Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. ASP-DAC 2008: 772-775 - [c159]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. DAC 2008: 566-569 - [c158]Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong:
MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562 - [c157]Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong:
A novel performance driven power gating based on distributed sleep transistor network. ACM Great Lakes Symposium on VLSI 2008: 255-260 - [c156]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Gate planning during placement for gated clock network. ICCD 2008: 128-133 - [c155]Weixiang Shen, Yici Cai, Xianlong Hong:
Leakage power optimization for clock network using dual-Vth technology. ISCAS 2008: 2769-2772 - [c154]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity and register placement aware gated clock network design. ISPD 2008: 182-189 - [c153]Haixia Yan, Qiang Zhou, Xianlong Hong:
Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. ISQED 2008: 289-292 - [c152]Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong:
DFM Based Detailed Routing Algorithm for ECP and CMP. ISQED 2008: 357-360 - [c151]Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong:
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876 - [c150]Yibo Wang, Yici Cai, Xianlong Hong:
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. ISVLSI 2008: 221-226 - [c149]Yanming Jia, Yici Cai, Xianlong Hong:
Full-chip routing system for reducing Cu CMP & ECP variation. SBCCI 2008: 10-15 - 2007
- [j52]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Voltage Island Generation in Cell Based Dual-Vdd Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(1): 267-273 (2007) - [j51]Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou:
Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 1028-1037 (2007) - [j50]Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu:
An efficient quadratic placement based on search space traversing technology. Integr. 40(3): 253-260 (2007) - [j49]Yaoguang Wei, Sheqin Dong, Xianlong Hong:
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. Integr. 40(4): 406-419 (2007) - [j48]Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Partitioning-based decoupling capacitor budgeting via sequence of linear programming. Integr. 40(4): 516-524 (2007) - [j47]Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong:
A Yield-Driven Gridless Router. J. Comput. Sci. Technol. 22(5): 653-660 (2007) - [j46]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - [j45]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong:
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 680-692 (2007) - [j44]Tom Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan:
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2073-2079 (2007) - [c148]Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 - [c147]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - [c146]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang:
Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. ASP-DAC 2007: 367-372 - [c145]Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong:
Logic and Layout Aware Voltage Island Generation for Low Power Design. ASP-DAC 2007: 666-671 - [c144]Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan:
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach. ASP-DAC 2007: 751-756 - [c143]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c142]Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang:
Simultaneous Switching Noise Consideration for Power/Ground Network Optimization. CAD/Graphics 2007: 332-337 - [c141]Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong:
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics 2007: 338-343 - [c140]Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical model order reduction for interconnect circuits considering spatial correlations. DATE 2007: 1508-1513 - [c139]Yanming Jia, Yici Cai, Xianlong Hong:
Dummy fill aware buffer insertion during routing. ACM Great Lakes Symposium on VLSI 2007: 31-36 - [c138]Xinjie Wei, Yici Cai, Xianlong Hong:
Physical aware clock skew rescheduling. ACM Great Lakes Symposium on VLSI 2007: 473-476 - [c137]Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 - [c136]Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong:
New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575 - [c135]Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong:
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. ICCAD 2007: 48-53 - [c134]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 - [c133]Xinjie Wei, Yici Cai, Xianlong Hong:
Effective Acceleration of Iterative Slack Distribution Process. ISCAS 2007: 1077-1080 - [c132]Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai:
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. ISCAS 2007: 2040-2043 - [c131]Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 - [c130]Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou:
Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. ISCAS 2007: 3411-3414 - [c129]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture. ISQED 2007: 299-304 - [c128]Yici Cai, Bin Liu, Jin Shi, Qiang Zhou, Xianlong Hong:
Power Delivery Aware Floorplanning for Voltage Island Designs. ISQED 2007: 350-355 - [c127]Hongjie Bai, Sheqin Dong, Xianlong Hong:
Congestion Driven Buffer Planning for X-Architecture. ISQED 2007: 835-840 - [c126]Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 - [c125]Hailong Yao, Yici Cai, Xianlong Hong:
CMP-aware Maze Routing Algorithm for Yield Enhancement. ISVLSI 2007: 239-244 - [c124]Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction. ISVLSI 2007: 383-388 - [c123]Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 - 2006
- [j43]Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu:
Time-domain analysis methodology for large-scale RLC circuits and its applications. Sci. China Ser. F Inf. Sci. 49(5): 665-680 (2006) - [j42]Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. Integr. 39(4): 457-473 (2006) - [j41]Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan:
ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21(1): 147-152 (2006) - [j40]Yici Cai, Bin Liu, Yan Xiong, Qiang Zhou, Xianlong Hong:
Priority-Based Routing Resource Assignment Considering Crosstalk. J. Comput. Sci. Technol. 21(6): 913-921 (2006) - [j39]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j38]Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2402-2412 (2006) - [j37]Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design. IEEE Trans. Circuits Syst. II Express Briefs 53-II(4): 309-313 (2006) - [j36]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [j35]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1007-1011 (2006) - [j34]Yici Cai, Jingjing Fu, Xianlong Hong, Sheldon X.-D. Tan, Zuying Luo:
Power/Ground Network Optimization Considering Decap Leakage Currents. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1012-1016 (2006) - [j33]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Multilevel Routing With Redundant Via Insertion. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1148-1152 (2006) - [j32]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j31]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006) - [j30]Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong:
Legitimate Skew Clock Routing with Buffer Insertion. J. VLSI Signal Process. 42(2): 107-116 (2006) - [c122]Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 - [c121]Xianlong Hong, Yici Cai, Hailong Yao, Duo Li:
DFM-aware Routing for Yield Enhancement. APCCAS 2006: 1091-1094 - [c120]Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong:
Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. APCCAS 2006: 1635-1638 - [c119]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. ASP-DAC 2006: 582-587 - [c118]Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan:
DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC 2006: 618-623 - [c117]Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC 2006: 630-635 - [c116]Di Long, Xianlong Hong, Sheqin Dong:
Signal-path driven partition and placement for analog circuit. ASP-DAC 2006: 694-699 - [c115]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong:
Efficient early stage resonance estimation techniques for C4 package. ASP-DAC 2006: 826-831 - [c114]Hailong Yao, Subarna Sinha, Charles C. Chiang, Xianlong Hong, Yici Cai:
Efficient process-hotspot detection using range pattern matching. ICCAD 2006: 625-632 - [c113]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
Buffer planning based on block exchanging. ISCAS 2006 - [c112]Sheqin Dong, Shuyi Zheng, Xianlong Hong:
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. ISCAS 2006 - [c111]Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang:
A novel technique integrating buffer insertion into timing driven placement. ISCAS 2006 - [c110]Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu:
High performance clock routing in X-architecture. ISCAS 2006 - [c109]Yibo Wang, Yici Cai, Xianlong Hong:
Performance and power aware buffered tree construction. ISCAS 2006 - [c108]Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu:
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ISCAS 2006 - [c107]Hailong Yao, Yici Cai, Xianlong Hong:
Congestion-driven W-shape multilevel full-chip routing framework. ISCAS 2006 - [c106]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong:
A novel low-power physical design methodology for MTCMOS. ISCAS 2006 - [c105]Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan:
An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ISPD 2006: 48-55 - [c104]Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong:
High accurate pattern based precondition method for extremely large power/ground grid analysis. ISPD 2006: 108-113 - [c103]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 - [c102]Xinjie Wei, Yici Cai, Xianlong Hong:
Clock Skew Scheduling Under Process Variations. ISQED 2006: 237-242 - [c101]Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming. ISQED 2006: 272-277 - [c100]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. JCIS 2006 - [c99]Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong:
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. JCIS 2006 - [c98]Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong:
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. JCIS 2006 - 2005
- [j29]Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu:
Reliable buffered clock tree routing algorithm with process variation tolerance. Sci. China Ser. F Inf. Sci. 48(5): 670-680 (2005) - [j28]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk and Congestion Driven Layer Assignment Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1565-1572 (2005) - [j27]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Computation for the Hybrid Structured Clock Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(7): 1964-1970 (2005) - [j26]Jingyu Xu, Xianlong Hong, Tong Jing:
Timing-Driven Global Routing with Efficient Buffer Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(11): 3188-3195 (2005) - [j25]Yongqiang Lu, Chin Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3405-3411 (2005) - [j24]Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong:
Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain. J. Comput. Sci. Technol. 20(2): 224-230 (2005) - [j23]Hailong Yao, Yici Cai, Qiang Zhou, Xianlong Hong:
Crosstalk-Aware Routing Resource Assignment. J. Comput. Sci. Technol. 20(2): 231-236 (2005) - [j22]Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong:
Shielding Area Optimization Under the Solution of Interconnect Crosstalk. J. Comput. Sci. Technol. 20(6): 901-906 (2005) - [j21]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [j20]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1066-1075 (2005) - [c97]Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan:
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005: 198-203 - [c96]Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
The polygonal contraction heuristic for rectilinear Steiner tree construction. ASP-DAC 2005: 1-6 - [c95]Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan:
An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC 2005: 7-12 - [c94]Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Analysis of buffered hybrid structured clock networks. ASP-DAC 2005: 93-98 - [c93]Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu, Yongqiang Lu:
Clock network minimization methodology based on incremental placement. ASP-DAC 2005: 99-102 - [c92]Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC 2005: 115-120 - [c91]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Register placement for low power clock network. ASP-DAC 2005: 588-593 - [c90]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
VLSI on-chip power/ground network optimization considering decap leakage currents. ASP-DAC 2005: 735-738 - [c89]Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu:
Relaxed hierarchical power/ground grid analysis. ASP-DAC 2005: 1090-1093 - [c88]Renshen Wang, Sheqin Dong, Xianlong Hong:
An improved P-admissible floorplan representation based on Corner Block List. ASP-DAC 2005: 1115-1118 - [c87]Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu:
LFF algorithm for heterogeneous FPGA floorplanning. ASP-DAC 2005: 1123-1126 - [c86]Rong Liu, Sheqin Dong, Xianlong Hong:
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. CAD/Graphics 2005: 6 - [c85]Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175 - [c84]Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. DAC 2005: 176-181 - [c83]Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen:
A New Buffer Planning Algorithm Based on Room Resizing. EUC 2005: 291-299 - [c82]Xiren Wang, Wenjian Yu, Zeyi Wang, Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction. ACM Great Lakes Symposium on VLSI 2005: 84-87 - [c81]Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou:
Improved multilevel routing with redundant via placement for yield and reliability. ACM Great Lakes Symposium on VLSI 2005: 143-146 - [c80]Rong Liu, Sheqin Dong, Xianlong Hong:
Fixed-outline floorplanning based on common subsequence. ACM Great Lakes Symposium on VLSI 2005: 156-159 - [c79]Qinglang Luo, Xianlong Hong, Qiang Zhou, Yici Cai:
A new algorithm for layout of dark field alternating phase shifting masks. ACM Great Lakes Symposium on VLSI 2005: 221-224 - [c78]Lijuan Luo, Qiang Zhou, Xianlong Hong, Hanbin Zhou:
Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. ICCSA (4) 2005: 896-905 - [c77]Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu:
A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS 2005: 275-286 - [c76]Yici Cai, Bin Liu, Xiong Yan, Qiang Zhou, Xianlong Hong:
A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. ICNC (3) 2005: 181-184 - [c75]Yici Cai, Yibo Wang, Xianlong Hong:
A global interconnect optimization algorithm under accurate delay model using solution space smoothing. ISCAS (1) 2005: 93-96 - [c74]Yiqian Zhang, Xianlong Hong, Yici Cai:
An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models. ISCAS (1) 2005: 97-100 - [c73]Xinjie Wei, Yici Cai, Xianlong Hong:
Zero skew clock routing with tree topology construction using simulated annealing method. ISCAS (1) 2005: 101-104 - [c72]Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213 - [c71]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c70]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
Integrated routing resource assignment for RLC crosstalk minimization. ISCAS (2) 2005: 1871-1874 - [c69]Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani:
Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886 - [c68]Jingyu Xu, Xianlong Hong, Tong Jing:
Timing-driven global routing with efficient buffer insertion. ISCAS (3) 2005: 2449-2452 - [c67]Di Long, Xianlong Hong, Sheqin Dong:
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. ISCAS (3) 2005: 2999-3002 - [c66]Yunfeng Wang, Jinian Bian, Xianlong Hong:
Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) 2005: 5641-5644 - [c65]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c64]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani:
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233 - [c63]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c62]Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547 - [c61]Jingyu Xu, Xianlong Hong, Tong Jing, Yang Yang:
Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design. ISQED 2005: 616-621 - [c60]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - [c59]Yici Cai, Bin Liu, Qiang Zhou, Xianlong Hong:
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. PATMOS 2005: 257-266 - [c58]Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan:
Efficient Simulation of Power/Ground Networks with Package and Vias. PATMOS 2005: 318-328 - [c57]Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan:
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS 2005: 344-353 - [c56]Yibo Wang, Yici Cai, Xianlong Hong:
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. VLSI Design 2005: 91-96 - 2004
- [j19]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j18]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j17]Yongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong:
Leakage Current Estimation of CMOS Circuit with Stack Effect. J. Comput. Sci. Technol. 19(5): 708-717 (2004) - [j16]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [j15]Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 358-365 (2004) - [j14]Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1086-1094 (2004) - [j13]Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 228-233 (2004) - [j12]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c55]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery. ASP-DAC 2004: 505-510 - [c54]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c53]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - [c52]Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu:
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design. ASP-DAC 2004: 677-682 - [c51]Qi Zhu, Hai Zhou, Tong Jing, Xianlong Hong, Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs. ASP-DAC 2004: 687-690 - [c50]Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan:
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. ICCD 2004: 344-349 - [c49]Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu:
Module placement based on quadratic programming and rectangle packing using less flexibility first principle. ISCAS (5) 2004: 61-64 - [c48]Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He:
Performance and RLC crosstalk driven global routing. ISCAS (5) 2004: 65-68 - [c47]Changqi Yang, Xianlong Hong, Hannah Honghua Yang, Qiang Zhou, Yici Cai, Yongqiang Lu:
Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. ISCAS (5) 2004: 81-84 - [c46]Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong:
Layer assignment algorithm for RLC crosstalk minimization. ISCAS (5) 2004: 85-88 - [c45]Hailong Yao, Qiang Zhou, Xianlong Hong, Yici Cai:
Crosstalk driven routing resource assignment. ISCAS (5) 2004: 89-92 - [c44]Weikun Guo, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong:
Partial random walk for large linear network analysis. ISCAS (5) 2004: 173-177 - [c43]Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou:
Algorithm for yield driven correction of layout. ISCAS (5) 2004: 241-245 - [c42]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) 2004: 297-300 - [c41]Meng Zhao, Xinjie Wei, Yici Cai, Xianlong Hong:
Quick and effective buffered legitimate skew clock routing. ISCAS (5) 2004: 337-340 - [c40]Zhu Pan, Yici Cai, Sheldon X.-D. Tan, Zuying Luo, Xianlong Hong:
Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling. ISQED 2004: 63-68 - [c39]Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441 - [c38]Yin Wang, Xianlong Hong, Tong Jing, Yang Yang, Xiaodong Hu, Guiying Yan:
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design. PATMOS 2004: 442-452 - 2003
- [j11]Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu:
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3136-3147 (2003) - [j10]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3158-3167 (2003) - [j9]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An efficient hierarchical timing-driven Steiner tree algorithm for global routing. Integr. 35(2): 69-84 (2003) - [j8]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
FaSa: A Fast and Stable Quadratic Placement Algorithm. J. Comput. Sci. Technol. 18(3): 318-324 (2003) - [j7]Tong Jing, Xianlong Hong, Haiyun Bao, Jingyu Xu, Jun Gu:
SSTT: Efficient Local Search for GSI Global Routing. J. Comput. Sci. Technol. 18(5): 632-640 (2003) - [j6]Xianlong Hong, Tong Jing, Jingyu Xu, Haiyun Bao, Jun Gu:
CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing. J. Comput. Sci. Technol. 18(6): 732-738 (2003) - [j5]Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu:
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. J. Comput. Sci. Technol. 18(6): 739-746 (2003) - [c37]Taotao Lu, Zeyi Wang, Xianlong Hong:
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction. ASP-DAC 2003: 255-260 - [c36]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c35]Zhuoyuan Li, Weimin Wu, Xianlong Hong:
Congestion driven incremental placement algorithm for standard cell layout. ASP-DAC 2003: 723-728 - [c34]Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu:
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. ASP-DAC 2003: 741-744 - [c33]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
A path-based timing-driven quadratic placement algorithm. ASP-DAC 2003: 745-748 - [c32]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC 2003: 834-839 - [c31]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. ASP-DAC 2003: 847-850 - [c30]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c29]Wenjian Yu, Zeyi Wang, Xianlong Hong:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. ICCD 2003: 58-63 - [c28]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c27]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c26]Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu:
Algorithms for analog VLSI 2D stack generation and block merging. ISCAS (4) 2003: 716-719 - [c25]Yongqiang Lu, Xianlong Hong, Wenting Hou, Weimin Wu, Yici Cai:
Combining clustering and partitioning in quadratic placement. ISCAS (4) 2003: 720-723 - [c24]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - 2002
- [j4]Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior. Sci. China Ser. F Inf. Sci. 45(4): 310-320 (2002) - [j3]Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) - [c23]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Jun Gu:
A novel and efficient timing-driven global router for standard cell layout design based on critical network concept. ISCAS (1) 2002: 165-168 - [c22]Shuzhou Fang, Zeyi Wang, Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. ASP-DAC/VLSI Design 2002: 305-310 - [c21]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - [c20]Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. ASP-DAC/VLSI Design 2002: 473-478 - 2001
- [j2]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [c19]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c18]Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu:
VLSI block placement using less flexibility first principles. ASP-DAC 2001: 601-604 - [c17]Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao:
A new congestion-driven placement algorithm based on cell inflation. ASP-DAC 2001: 605-608 - [c16]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 - [c15]Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD 2001: 153-157 - 2000
- [c14]Yan Zhang, Baohua Wang, Yici Cai, Xianlong Hong:
Area routing oriented hierarchical corner stitching with partial bin. ASP-DAC 2000: 105-110 - [c13]Hong Yu, Xianlong Hong, Yici Cai:
MMP: a novel placement algorithm for combined macro block and standard cell layout design. ASP-DAC 2000: 271-276 - [c12]Jiangchun Gu, Zeyi Wang, Xianlong Hong:
Hierarchical computation of 3-D interconnect capacitance using direct boundary element method. ASP-DAC 2000: 447-452 - [c11]Shuzhou Fang, Xiaobo Tang, Zeyi Wang, Xianlong Hong:
A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section. ASP-DAC 2000: 453-456 - [c10]Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12
1990 – 1999
- 1999
- [c9]Xiaohai Wu, Changge Qiao, Xianlong Hong:
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. ASP-DAC 1999: 21- - [c8]Jinsong Hou, Zeyi Wang, Xianlong Hong:
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. ASP-DAC 1999: 93- - [c7]Haiyun Bao, Xianlong Hong, Yici Cai:
A New Global Routing Algorithm Independent Of Net Ordering. ASP-DAC 1999: 245-248 - [c6]Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai:
A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC 1999: 249-252 - [c5]Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong:
FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC 1999: 363- - 1997
- [j1]Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1323-1331 (1997) - [c4]Tianming Kong, Xianlong Hong, Changge Qiao:
VEAP: Global optimization based efficient algorithm for VLSI placement. ASP-DAC 1997: 277-280 - 1993
- [c3]Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing. DAC 1993: 177-181 - [c2]Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh:
An Efficient Timing-Driven Global Routing Algorithm. DAC 1993: 596-600 - 1992
- [c1]Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC 1992: 530-535
Coauthor Index
[j73] [j72] [j71] [j67] [c178] [c176] [c175] [c170] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j57] [j55] [j54] [j53] [c165] [c163] [c162] [c161] [c158] [c157] [c156] [c155] [c154] [c152] [c150] [c149] [j52] [j51] [j50] [j48] [j47] [j45] [c146] [c145] [c144] [c142] [c140] [c139] [c138] [c136] [c135] [c133] [c132] [c129] [c128] [c125] [c124] [j43] [j40] [j38] [j35] [j34] [j33] [j32] [j30] [c121] [c120] [c119] [c115] [c114] [c111] [c110] [c109] [c107] [c106] [c104] [c102] [c101] [j29] [j28] [j27] [j25] [j24] [j23] [j22] [c94] [c93] [c91] [c90] [c89] [c85] [c84] [c81] [c79] [c76] [c75] [c74] [c73] [c70] [c64] [c62] [c59] [c58] [c56] [j19] [j18] [j14] [j13] [j12] [c55] [c54] [c53] [c50] [c47] [c46] [c45] [c43] [c42] [c41] [c40] [c39] [j10] [j9] [j8] [c36] [c33] [c32] [c31] [c30] [c28] [c27] [c25] [c24] [j4] [j3] [c23] [c21] [c20] [j2] [c19] [c17] [c16] [c15] [c14] [c13] [c10] [c7] [c6]
[j77] [c181] [c173] [c169] [c166] [c164] [c160] [j49] [c148] [c143] [c137] [c131] [c127] [c126] [c123] [j39] [j36] [c122] [c116] [c113] [c112] [c108] [c100] [c99] [c98] [j21] [c88] [c87] [c86] [c83] [c80] [c72] [c71] [c69] [c67] [c65] [c63] [c60] [j19] [j18] [j16] [j13] [j12] [c54] [c53] [c49] [j11] [j5] [c36] [c34] [c30] [c28] [c27] [c26] [c24] [j3] [c21] [j2] [c19] [c18] [c16] [c10]
[j75] [j73] [j68] [j67] [c176] [c170] [j65] [j63] [c165] [c163] [c158] [c157] [c153] [c152] [j52] [j50] [j47] [j46] [c146] [c145] [c143] [c141] [c136] [c134] [c132] [c130] [c128] [j40] [j35] [j33] [j32] [j31] [c120] [c119] [c111] [c106] [c103] [j28] [j27] [j25] [j23] [j22] [c94] [c93] [c91] [c84] [c81] [c79] [c78] [c77] [c76] [c70] [c64] [c59] [c50] [c47] [c46] [c45] [c43] [c42]
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last updated on 2025-01-09 13:03 CET by the dblp team
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