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Katsuro Sasaki
1990 – 1999
- 1997
- [j15]Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki:
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5(4): 417-424 (1997) - 1996
- [c1]Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki:
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED 1996: 353-358 - 1995
- [j14]Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30(3): 251-257 (1995) - [j13]Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki:
Half-swing clocking scheme for 75% power saving in clocking circuitry. IEEE J. Solid State Circuits 30(4): 432-435 (1995) - [j12]Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome:
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits 30(4): 487-490 (1995) - [j11]Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome:
Trends in low-power RAM circuit technologies. Proc. IEEE 83(4): 524-543 (1995) - 1994
- [j10]Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki:
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits 29(4): 411-418 (1994) - 1993
- [j9]Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki:
A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell. IEEE J. Solid State Circuits 28(11): 1125-1130 (1993) - [j8]Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE J. Solid State Circuits 28(11): 1145-1151 (1993) - 1992
- [j7]Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima:
A 1.7-V adjustable I/O interface for low-voltage fast SRAMs. IEEE J. Solid State Circuits 27(4): 674-677 (1992) - [j6]Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima:
A voltage down converter with submicroampere standby current for low-power static RAMs. IEEE J. Solid State Circuits 27(6): 920-926 (1992) - [j5]Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu:
A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. IEEE J. Solid State Circuits 27(11): 1511-1518 (1992) - [j4]Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki:
A 1-V TFT-load SRAM using a two-step word-voltage method. IEEE J. Solid State Circuits 27(11): 1519-1524 (1992) - [j3]Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki:
A 1.5-V full-swing BiCMOS logic circuit. IEEE J. Solid State Circuits 27(11): 1568-1574 (1992) - 1990
- [j2]Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato:
A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current. IEEE J. Solid State Circuits 25(5): 1075-1081 (1990)
1980 – 1989
- 1989
- [j1]Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo:
A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits 24(5): 1219-1225 (1989)
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