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- unicode name: 戴葵
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2020 – today
- 2024
[j14]Meilin Wan
, Zhen Zhang, Yin Zhang, Zhangqing He, Haoshuang Gu, Kui Dai, Xuecheng Zou:
A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection. IEEE J. Solid State Circuits 59(7): 2330-2344 (2024)
2010 – 2019
- 2019
- [j13]Jinli Rao, Tianyong Ao, Kui Dai, Xuecheng Zou:
ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management. IEEE Comput. Archit. Lett. 18(2): 115-118 (2019) - 2018
- [j12]Jinli Rao, Tianyong Ao, Shu Xu, Kui Dai, Xuecheng Zou:
Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor. IEICE Trans. Inf. Syst. 101-D(11): 2698-2705 (2018) - [j11]Zhangqing He, Meilin Wan, Jie Deng, Chuang Bai, Kui Dai:
A Reliable Strong PUF Based on Switched-Capacitor Circuit. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1073-1083 (2018) - 2016
- [j10]Jinli Rao, Zhangqing He, Shu Xu, Kui Dai, Xuecheng Zou:
BFWindow: Speculatively Checking Data Property Consistency against Buffer Overflow Attacks. IEICE Trans. Inf. Syst. 99-D(8): 2002-2009 (2016) - [j9]Meilin Wan, Wang Liao, Kui Dai, Xuecheng Zou:
A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 156-160 (2016) - [j8]Chuang Bai, Xuecheng Zou, Kui Dai:
A Novel Thyristor-Based Silicon Physical Unclonable Function. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 290-300 (2016) - 2015
- [j7]Meilin Wan, Zhenzhen Zhang, Wang Liao, Kui Dai, Xuecheng Zou:
A 2/3 Dual-Modulus Prescaler Using Complementary Clocking NMOS-Like Blocks. J. Circuits Syst. Comput. 24(7): 1550109:1-1550109:23 (2015) - [j6]Meilin Wan, Zhangqing He, Shuang Han, Kui Dai, Xuecheng Zou:
An Invasive-Attack-Resistant PUF Based On Switched-Capacitor Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2024-2034 (2015) - [c60]Meilin Wan, Zhenzhen Zhang, Kui Dai, Xuecheng Zou:
A 1-V 2.5-ppm/°C second-order compensated bandgap reference. ASICON 2015: 1-4 - 2014
- [j5]Libo Huang, Li Shen, Yashuai Lv, Zhiying Wang, Kui Dai:
Mac or Non-MAC: not a Problem. J. Circuits Syst. Comput. 23(5) (2014) - [c59]Tianyong Ao, Zhangqing He, Jinli Rao, Kui Dai, Xuecheng Zou:
A Compact Hardware Implementation of SM3 Hash Function. TrustCom 2014: 846-850 - 2011
- [j4]Dan Wu, Xuecheng Zou, Kui Dai, Jinli Rao, Pan Chen, Zhaoxia Zheng:
Implementation and evaluation of parallel FFT on Engineering and Scientific Computation Accelerator (ESCA) architecture. J. Zhejiang Univ. Sci. C 12(12): 976-989 (2011) - [c58]Wanghui Zou, Xiaofei Chen, Jianming Lei, Kui Dai, Xuecheng Zou:
An area-efficient 5GHz/10GHz dual-mode VCO with coupled helical inductors in 0.13-UM CMOS technology. CCECE 2011: 512-515 - 2010
- [j3]Dongsheng Liu, Xuecheng Zou, Kui Dai, Si-Zheng Li, Xue-Mei Hui, Yao Liu, Qiaoling Tong:
New design of RF rectifier for passive UHF RFID transponders. Microelectron. J. 41(1): 51-55 (2010) - [c57]Pan Chen, Kui Dai, Dan Wu, Jinli Rao, Xuecheng Zou:
The parallel algorithm implementation of matrix multiplication based on ESCA. APCCAS 2010: 1091-1094 - [c56]Dan Wu, Kui Dai, Xuecheng Zou, Jinli Rao, Pan Chen:
A High Efficient On-Chip Interconnection Network in SIMD CMPs. ICA3PP (1) 2010: 149-162
2000 – 2009
- 2009
- [c55]Sheng Ma, Libo Huang, Zhiying Wang, Kui Dai:
Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization. NAS 2009: 379-385 - 2008
- [j2]Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang:
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique. J. Electron. Test. 24(1-3): 57-65 (2008) - [c54]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Memory System Design for a Multi-core Processor. CISIS 2008: 601-606 - [c53]Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai:
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. DAC 2008: 630-633 - [c52]Rui Gong, Kui Dai, Zhiying Wang:
A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors. DFT 2008: 184-192 - [c51]Rui Gong, Kui Dai, Zhiying Wang:
Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. ICYCS 2008: 148-153 - [c50]Xinbiao Gan, Kui Dai, Zhiying Wang:
Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization. ICYCS 2008: 200-205 - [c49]Lei Wang, Zhiying Wang, Kui Dai:
Performance Bound Analysis and Retiming of Timed Circuits. ICYCS 2008: 212-217 - [c48]Jianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang:
The P2P Communication Model for a Local Memory based Multi-core Processor. ICYCS 2008: 1354-1359 - [c47]Xinbiao Gan, Kui Dai, Libo Huang, Li Shen, Zhiying Wang:
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. MUE 2008: 83-86 - [c46]Rui Gong, Kui Dai, Zhiying Wang:
Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. PRDC 2008: 273-280 - [c45]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Hierarchical memory system design for a heterogeneous multi-core processor. SAC 2008: 1504-1508 - [c44]Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang:
Control flow checking and recovering based on 8051 architecture. SAC 2008: 1550-1551 - 2007
- [c43]Yong Li, Zhiying Wang, Kui Dai:
A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. CIT 2007: 817-822 - [c42]Yong Li, Zhiying Wang, Xue-mi Zhao, Jian Ruan, Kui Dai:
Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. Asia-Pacific Computer Systems Architecture Conference 2007: 354-363 - [c41]Gang Jin, Lei Wang, Zhiying Wang, Kui Dai:
An Optimal Design Method for De-synchronous Circuit Based on Control Graph. APPT 2007: 70-79 - [c40]Libo Huang, Li Shen, Kui Dai, Zhiying Wang:
A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. IEEE Symposium on Computer Arithmetic 2007: 69-76 - [c39]Yong Li, Zhiying Wang, Jian Ruan, Kui Dai:
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor. HPCC 2007: 168-179 - [c38]Jian Ruan, Zhiying Wang, Kui Dai, Yong Li:
Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra. International Conference on Computational Science (4) 2007: 251-258 - [c37]Wang Jingxin, Zhiying Wang, Kui Dai:
Security Event Management System based on Mobile Agent Technology. ISI 2007: 166-171 - [c36]Ming-che Lai, Jianjun Guo, Lv Yasuai, Kui Dai, Zhiying Wang:
The Research of an Embedded Processor Element for Multimedia Domain. MCAM 2007: 267-276 - [c35]Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen:
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. MUE 2007: 633-637 - [c34]Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. PATMOS 2007: 43-52 - [c33]Jian Ruan, Zhiying Wang, Kui Dai, Yong Li:
Design and Test of Self-checking Asynchronous Control Circuit. PATMOS 2007: 320-329 - 2006
- [j1]Yong Li, Lei Wang, Rui Gong, Kui Dai, Zhiying Wang:
Research and Implementation of a 32-Bit Asynchronous Multiplier. J. Comput. Res. Dev. 43(12): 2152-2157 (2006) - [c32]Wei Chen, Rui Gong, Kui Dai, Fang Liu, Zhiying Wang:
Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems. CIT 2006: 175 - [c31]Lei Wang, Zhiying Wang, Kui Dai:
An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings. CIT 2006: 244 - [c30]Jianjun Guo, Kui Dai, Zhiying Wang:
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. Asia-Pacific Computer Systems Architecture Conference 2006: 359-365 - [c29]Lei Wang, Zhiying Wang, Kui Dai:
Cycle Period Analysis and Optimization of Timed Circuits. Asia-Pacific Computer Systems Architecture Conference 2006: 502-508 - [c28]Yuan-man Tong, Zhiying Wang, Kui Dai, Hongyi Lu:
Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. Inscrypt 2006: 66-77 - [c27]Hong Yue, Kui Dai, Zhiying Wang:
A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications. ESA 2006: 100-104 - [c26]Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wang:
Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy. ESA 2006: 183-190 - [c25]Rui Gong, Wei Chen, Fang Liu, Kui Dai, Zhiying Wang:
Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. DFT 2006: 184-196 - [c24]Jianjun Guo, Kui Dai, Zhiying Wang:
A High Performance Heterogeneous Architecture and Its Optimization Design. HPCC 2006: 300-309 - [c23]Hong Yue, Zhiying Wang, Kui Dai:
A Heterogeneous Embedded MPSoC for Multimedia Applications. HPCC 2006: 591-600 - [c22]Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang:
A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. ICME 2006: 369-372 - [c21]Jing-Xin Wang, Zhiying Wang, Kui Dai:
Intrusion Alert Analysis Based on PCA and the LVQ Neural Network. ICONIP (3) 2006: 217-224 - [c20]Jing-Xin Wang, Zhiying Wang, Kui Dai:
A PCA-LVQ Model for Intrusion Alert Analysis. ISI 2006: 715-716 - [c19]Fangyong Hou, Hongjun He, Zhiying Wang, Kui Dai:
An Efficient Way to Build Secure Disk. ISPEC 2006: 290-301 - [c18]Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai:
A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. VLSI-SoC 2006: 216-221 - 2005
- [c17]Jianjun Guo, Kui Dai, Yun Cheng, Zhiying Wang:
Research on Fast Block Participation Mode Selection Algorithm in H.264. ACIS-ICIS 2005: 111-113 - [c16]Yun Cheng, Kui Dai, Zhiying Wang, Jianjun Guo:
A Fast Motion Estimation Algorithm Based on Diamond and Simplified Square Search Patterns. CIARP 2005: 440-449 - [c15]Yun Cheng, Zhiying Wang, Jianjun Guo, Kui Dai:
Research on intra modes for inter-frame coding in H.264. CSCWD (2) 2005: 740-744 - [c14]Dan Wu, Zhiying Wang, Kui Dai:
Retargetable Machine-Description System: Multi-layer Architecture Approach. GCC 2005: 1161-1166 - [c13]Yun Cheng, Zhiying Wang, Kui Dai, Jianjun Guo:
A Fast Motion Estimation Algorithm Based on Diamond and Triangle Search Patterns. IbPRIA (1) 2005: 419-426 - [c12]Fang Liu, Kui Dai, Zhiying Wang, Jun Ma:
Research on Fuzzy Group Decision Making in Security Risk Assessment. ICN (2) 2005: 1114-1121 - [c11]Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang:
Design of a Configurable Embedded Processor Architecture for DSP Functions. ICPADS (2) 2005: 27-31 - [c10]Fangyong Hou, Zhiying Wang, Kui Dai, Yun Liu:
Protecting Mass Data Basing on Small Trusted Agent. ISPEC 2005: 362-373 - [c9]Jiangchun Ren, Kui Dai, Zhiying Wang:
Trust-Enhanced Alteration Scenario for Universal Computer. PRDC 2005: 275-280 - [c8]Fang Liu, Yong Chen, Kui Dai, Zhiying Wang, Zhiping Cai:
Research on Risk Probability Estimating Using Fuzzy Clustering for Dynamic Security Assessment. RSFDGrC (2) 2005: 539-547 - [c7]Jiangchun Ren, Kui Dai, Zhiying Wang, Xue-mi Zhao, Yuan-man Tong:
Design and Implementation a TPM Chip SUP320 by SOC. SEC 2005: 143-154 - 2004
- [c6]Lei Wang, Hongyi Lu, Kui Dai, Zhiying Wang:
TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC. Asia-Pacific Computer Systems Architecture Conference 2004: 126-136 - [c5]Fang Liu, Kui Dai, Zhiying Wang:
Improving Security Architecture Development Based on Multiple Criteria Decision Making. AWCC 2004: 214-218 - [c4]Yun Cheng, Zhiying Wang, Kui Dai, Jianjun Guo:
Analysis of Inter-Frame Coding Without Intra Modes in H.264. Eurographics Multimedia Workshop 2004: 77-86 - [c3]Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang:
A New Technique for Program Code Compression in Embedded Microprocessor. ICESS 2004: 158-164 - [c2]Jing-Xin Wang, Zhi-Ying Wang, Kui Dai:
A network intrusion detection system based on the artificial neural networks. InfoSecu 2004: 166-170 - [c1]Fang Liu, Kui Dai, Zhiying Wang:
Applying multiple criteria decision making to improve security architecture development. InfoSecu 2004: 244-246
Coauthor Index
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last updated on 2025-01-09 13:23 CET by the dblp team
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