TRISTAN

The TRISTAN Free Access Training on EDA tooling for RISC-V was a successful event at the RISC-V Summit Europe 2024! After a quick introduction to TRISTAN and its EDA tooling landscape, we covered three very relevant areas of EDA tooling for RISC-V. In the first part, MINRES gave us insights into Virtual Platform Modeling for RISC-V Systems in early design phases – touching several technologies such as Instruction Set Simulators (DBT-RISE for creating ISS and CoreDSL for ISA descriptions) and architectural modeling based on SystemC (e.g., SystemC Components Library and PySysC) by the example of developing an embedded trace unit “C-Trace” within TRISTAN. The second talk provided by the OpenHW Group showed how open-source verification methods and frameworks can be efficiently applied on the RISC-V core CVE2. Starting from an introduction into the RISC-V core CV32E20, CORE-V-verif was introduced for verification methodology and building a CVE2 testbench. Many practical steps were provided for running a full verification for CVE2. A third presentation concluded the training workshop by STMicroelectronics sharing their experiences with open-source and commercial EDA tools for RISC-V verification running through various verification activities – from code reviews, directed tests, random tests, formal verification, SW benchmark testing, and coverage and testbench qualification. The training material can be found on the TRISTAN webpage here: https://lnkd.in/ez7yMDzs

🚀 Thales proudly contributes to the TRISTAN and ISOLDE Project, reinforcing its Commitment to Open-Source and Pioneering RISC-V Innovation. #riscv #openHWGroup #cva6

TRISTAN partner Yongatek Microelectronics had a fantastic time at this year’s chip design contest in Antalya, Türkiye, which included analog chip design, RISC-V core design, and RISC-V-powered microcontroller design legs. As the competing students reach the finish line and got their awards in the Adana Teknofest, here are some highlights from the event: - A hundred teams consisting of graduate and undergraduate students have entered the competition, with twenty-one of them participating in the microcontroller design category run by Yongatek Microelectronics. - The goal of the competition was building an MCU around OpenHW Group’s CV32E40P core that had several technical requirements and executing a full RTL-to-GDS flow on it with either open-source or sponsored commercial EDA tools provided. - Eight of the teams totaling forty-two people made it to the finals and did their live presentations and FPGA demonstrations in the event venue. During the finals, all participants from all categories had four days to meet, interact, present, and discuss their designs in the event venue under the guidance of sixteen juries, with six of them being responsible from the microcontroller design category. - In the end of nine months, three of the teams managed to obtain GDS files; three of the teams successfully implemented a bootloader and got their designs up and running on an FPGA board.

🚀 Thales' Continued Commitment to Open Source and RISC-V Innovation.🚀 Thales Digital Identity and Security is still actively participating in European-funded projects TRISTAN & ISOLDE, alongside major players in the open-source and RISC-V communities Bosch France, CEA Grenoble, OpenHW Group, PULP Platform, ETH Zürich, Axelera AI, MU-Electronics. 🌍💻 Thanks to Chips JU and Bpifrance, we are driving innovation and contributing to the advancement of open technology ecosystems. Learn how RISC-V is reshaping the semiconductor landscape and why it’s a crucial part of Europe’s strategy in the latest article https://lnkd.in/evQFeNP6 🔗 #Thales #RISC-V #OpenSource #OpenHW #Innovation #TRISTAN #ISOLDE #Semiconductors #ChipsAct

🚀 Thales' Continued Commitment to Open-Source and RISC-V Innovation. Thales Digital Identity and Security is still actively participating in European-funded projects TRISTAN & ISOLDE, alongside major players in the open-source and RISC-V communities Bosch France, CEA Grenoble, OpenHW Group, PULP Platform, ETH Zürich, Axelera AI, MU-Electronics. 🌍💻 Thanks to Chips JU and Bpifrance, we are driving innovation and contributing to the advancement of open technology ecosystems. Learn how RISC-V is reshaping the semiconductor landscape and why it’s a crucial part of Europe’s strategy in the latest article https://lnkd.in/evQFeNP6 #Thales #RISC-V #OpenSource #OpenHW #Innovation #TRISTAN #ISOLDE #Semiconductors #ChipsAct

Have you already checked out Ara2? It's the first fully open-source vector processor supporting the RISC-V "V" 1.0 ISA. Designed to target data-parallel workloads, Ara2 brings cutting-edge  performance and energy efficiency to the table. In this paper, we present a novel open-source vector architecture  and  characterize its performance and power efficiency on a broad set of applications and workload conditions on single- and multi-core configurations.  Here are some key highlights from our work: Þ   Scalable Design: Ara2 supports the RISC-V "V" 1.0 ISA and comes  in different configurations, from 2 to 16 parallel processing units. Þ   Streamlined Microarchitecture: We show that Ara2 can be  physically implemented in all its configurations, thanks to ad-hoc  microarchitectural optimizations to its interconnects. Þ   Thorough Characterization: We study Ara2's performance on  multiple  kernels from machine learning, DSP, and linear algebra for  different  problem sizes. Ara2 reaches peaks of more than 97% of its maximum performance on real workloads. Þ   Single- and Multi-Core Solution: We study the performance/power trade-off of vector architectures of variable processing capabilities when running applications on single- and multi-core architectures.  Check out our paper here https://lnkd.in/e8t9FBpU  for a technical deep dive and more insights!

Check out this exciting position to join TRISTAN at OpenHW Group

TRISTAN Project Technical Conference 2024 Impressions and legacy As strong winds from north and heavy rains are hitting in these hours the city of #Graz and the surrounding region of #Steiermark and I can't enjoy one of my ritual weekend bicycles long-rides, I have time to think back to the surprisingly successful event held this week at Technische Universität Graz. Sitting on my couch, I'm only feeling now the fall-out of the few hours slept in the last days to give my 50 cents to the event. On Wednesday morning, few minutes before watching all attendees flooding the conference foyer and queuing up to get their badge, I was not imagining it would be so intense, engaging and full of learning and networking opportunities. Beside the presence of many TRISTAN partners, the hall was filled by young engineers coming from all Graz' district semiconductors companies and about fifty engineering students, not to mention a large number of participants remotely connected from all corners of Europe. A zest of the event is shown by the short movie masterfully created by Maximilian Steger. In the coming days, on TRISTAN website and its LinkedIn page we will make all public presentations available for the community of RISC-V aficionados. Feedback, questions and suggestions for next year's event (yes, there will be certainly another one) will always be welcome. Before closing, on behalf of all the attendees and the event drivers' team, I want to express again my greatest appreciation and thanks to all the young students of the Institute of Technical Informatics (#ITI) of #TUG, who supported us on the on-site logistic arrangements, the project website updates (https://lnkd.in/dNcNnhEV), the registration and mailing system, as well as on the event rooms equipment handling.

Looking back to TRISTAN technical conference in Graz After an intense one day and half long agenda, full of engaging technical presentations, tutorials and poster sessions, TRISTAN Project technical conference is heading now to a happy conclusion. Hosted by Technische Universität Graz (TUG) and cooperated with NXP Semiconductors Austria, the event has gathered more than one hundred in-presence attendees in the halls of the local #ITI, Institute of Technical Informatics, whereas almost the same number of experts, professionals and engineers to be was remotely connected. The program has been enriched by a series of keynotes from #TUG Vice-Rector Michael Monsberger, Andrea Gallo VP of RISC-V International, Davide Rossi associate professor at Alma Mater Studiorum – Università di Bologna and Patrick Pype, TRISTAN project main coordinator. In the coming days we will have time to collect feedback and follow up the talks with a list of actions points addressing new dissemination and collaboration opportunities within TRISTAN, as well as together with its siblings Chips Joint Undertaking funded projects focusing on the #RISCV and #OpenSource ecosystems growth. The event organizing team, represented by prof. Christian Steger (TUG), Marcus Borrmann and Tiberio Fanti (NXP Semiconductors Austria) would like to thank all those who have provided their priceless support in making this event possible and so rich of learning and networking opportunities. The excerpts from the conference are public and will be soon made available on TRISTAN Project webpages. We're looking forward to organizing out second project technical conference as soon as our deliverables will be ready for a demo.

RISC-V enthusiasts, see you in Graz !