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A 2-V 300-MHz 1-Mb current-sensed double-density SRAM ...
IEEE Xplore
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由 N Shibata 著作2001被引用 20 次 — This paper presents megabit-class high-speed and low-power embedded SRAM techniques for high data-throughput CMOS/SIMOX ASICs. In order to reduce the power ...
A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for ...
Semantic Scholar
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The authors have developed a 256-kb SRAM for solar-power-operated digital equipment using MTCMOS circuits and silicon-on-insulator (SOI) devices, ...
Predictable Power Saving Memory Controller Circuit ...
ResearchGate
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ResearchGate
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2024年10月22日 — A 2-V 300MHz 1Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. Article. Oct 2001. Naoya Shibata · M ...
Nobutaro Shibata
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2024年4月25日 — A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. IEEE J. Solid State Circuits 36(10): 1524-1537 ...
Takako Ishihara
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2024年4月25日 — A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. IEEE J. Solid State Circuits 36(10): 1524-1537 ...
A current-sensed high-speed and low-power first-in-first-out ...
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High-speed and low-power CMOS memory techniques specialized for FIFO operation are presented and a size-configurable architecture using the tile methodology ...
Memory-cell-array configurations: (a) conventional ...
ResearchGate
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ResearchGate
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A 2-V 300MHz 1Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs. Article. Oct 2001; IEEE J SOLID-ST CIRC. Nobutaro ...
Process variations aware area efficient negative bit-line voltage ...
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Negative bit-line scheme during write has been found one of the most promising write-assist solutions. A new low power, negative bit-line scheme is presented.
Schottky diode static random access memory (DSRAM) ...
Google Patents
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Google Patents
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2001 A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-/spl mu/m CMOS/SIMOX ASICs. EP3149736A1 2017-04-05 Write assist sram circuits ...
A Data Retention Gated-Ground Cache for Low Power
UC Irvine
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由 A Agarwal 著作2002被引用 229 次 — In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories ...
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