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A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm ...
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This paper describes a 6.4Gb/s data lane circuit in 65nm CMOS process. The data lane circuit consists of an offset cancellation continuous time linear ...
A 6.4 Gb/s data lane design for forwarded clock receiver in ...
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由 K Yu 著作2012 — This paper presents a design and simulation results of a data lane circuit in a forwarded clock receiver. Section II describes the overall design structure of ...
A 6.4 Gb/s data lane design for forwarded clock receiver in ...
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This paper describes a 6.4Gb/s data lane circuit in 65nm CMOS process that can compensate over 8 dB channel loss with offset-calibrated and low noise and is ...
A 6.4 Gb/s source synchronous receiver core with variable ...
ResearchGate
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This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can ...
Xuqiang Zheng_People--Tsinghua ICAS-IME
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[37] Kunzhi Yu,Ziqiang Wang,Xuan Ma,Xuqiang Zheng,Chun Zhang,Zhihua Wang, A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS, MWSCAS 2012, pp ...
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL- ...
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由 S Shin 著作2020被引用 5 次 — At the data rate of 6.4 Gb/s, the proposed. FC receiver achieves an energy efficiency of 0.45 pJ/bit. Index Terms—Delay-locked loop, forwarded-clock receiver,.
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A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT- ...
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An energy/area-efficient forwarded-clock receiver fabricated in a 28nm CMOS process that adopts a novel all-digital clock and data recovery (CDR) using a ...
Frank O'Mahony
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A 0.6 mW/Gb/s, 6.4–7.2 Gb/s serial link receiver using local injection-locked ring oscillators in 90 nm CMOS. K Hu, T Jiang, J Wang, F O'Mahony, PY Chiang. IEEE ...
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous ...
IBM Research
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由 R Reutemann 著作2010被引用 48 次 — This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.26.4 Gb/s.
A 6-Gbps dual-mode digital clock and data recovery circuit in ...
ACM Digital Library
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由 MK Jeon 著作2015被引用 2 次 — A 1.2pJ/b 6.4 Gb/s 8 + 1-lane forwarded-clock receiver with PVT ... A digital wideband CDR with ±15.6kppm frequency tracking at 8 Gb/s in 40 nm ...