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Design diversity for concurrent error detection in sequential ...
IEEE Xplore
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IEEE Xplore
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由 S Mitra 著作2001被引用 13 次 — Abstract: We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits.
Design diversity for concurrent error detection in sequential logic ...
ResearchGate
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ResearchGate
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We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits. We examine three different ...
DESIGN DIVERSITY FOR CONCURRENT ERROR DETECTION IN ...
ieeecomputer.org
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ieeecomputer.org
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Abstract. We present a technique using diverse duplication to implement concurrent error detection (CED) in sequential logic circuits.
Concurrent Error Detection for Combinational and ...
Purdue University
https://www.cs.purdue.edu › Drineas_ISQED_04
Purdue University
https://www.cs.purdue.edu › Drineas_ISQED_04
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由 S Almukhaizim 著作被引用 12 次 — In this paper, we examine a low-cost, zero-latency, non- intrusive CED method for restricted error models. The method is based on compaction of the circuit ...
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001
IEEE Computer Society
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IEEE Computer Society
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Design Diversity for Concurrent Error Detection in Sequential Logic Circuts pp. 0178. Early Error Detection in Systems-on-Chip for Fault-Tolerance and At ...
Techniques-for-estimation-of-design-diversity-for- ...
ResearchGate
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The adaptive Monte-. Carlo simulation technique provides accurate estimates of the design diversity metric; the number of simulations used to reach this ...
Concurrent error detection for combinational and sequential ...
Semantic Scholar
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Semantic Scholar
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A compaction-based CED method is examined, which employs a similar decomposition principle to alleviate synthesis limitations for restricted error models ...
Duplication-based concurrent error detection in ...
The University of Texas at Dallas
https://personal.utdallas.edu › papers › dfts02
The University of Texas at Dallas
https://personal.utdallas.edu › papers › dfts02
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由 T Verdel 著作被引用 48 次 — We propose a circuit that alleviates the difficulties associated with comparison synchronization and we introduce a methodology that enables detection of errors ...
Compaction-based concurrent error detection for digital ...
ScienceDirect.com
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ScienceDirect.com
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由 S Almukhaizim 著作2005被引用 13 次 — In this paper, we examine a low-cost, zero-latency, non-intrusive CED method for logic circuits. The method is based on compaction of the circuit outputs, ...
combinational logic synthesis for diversity in duplex systems
CiteSeerX
https://citeseerx.ist.psu.edu › document
CiteSeerX
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由 S Mitra 著作被引用 31 次 — We describe logic synthesis techniques for designing diverse implementations of combinational logic circuits in order to maximize the data integrity of diverse ...