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Estimating Architectural Resources and Performance for ...
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由 A Sharms 著作被引用 153 次 — In this paper we present a solution to the following problems related to architectural synthesis. Given an input specification and a perfomance constraint, ...
Estimating architectural resources and performance for ...
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由 A Sharma 著作1993被引用 153 次 — The authors present a solution to the following problems related to architectural synthesis. (1) Given an input specification and a performance constraint, ...
Estimating architectural resources and performance for ...
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由 A Sharma 著作1993被引用 153 次 — The two main steps performed during architectural synthesis are schedul- ing and binding which determine a major part of the total chip area requirements, and.
Estimating Architectural Resources and Performance for High- ...
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Realistic performance-constrained pipelining in high-level synthesis · Lower-bound performance estimation for the high-level synthesis scheduling problem.
Estimating architectural resources and performance for high-level ...
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Estimating architectural resources and performance for high-level synthesis applications. Sharma, A., Jain, R. Details · Contributors · Fields of science ...
Estimating Architectural Resources and Performance for High- ...
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Estimating Architectural Resources and Performance for High-Level Synthesis Applications DAC, 1993. DAC 1993 · DBLP · Scholar · DOI. Full names. Links ISxN.
Publication: Estimating architectural resources and performance ...
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Estimating architectural resources and performance for high-level synthesis applications. Alok Sharma Rajiv Jain. Published in: IEEE Trans. Very Large Scale ...
A hierarchical cost estimation technique for high level synthesis
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The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation ...
Estimation of BIST Resources During High-Level Synthesis
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由 I Parulkar 著作1998被引用 4 次 — Lower bound estimations of functional resources at various stages of high-level synthesis have been developed to guide synthesis algorithms toward optimal.
A comprehensive estimation technique for high-level synthesis
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Estimating Architectural Resources and Performance for High-Level Synthesis Applications · Alok SharmaR. Jain. Computer Science, Engineering. 30th ACM/IEEE ...