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[en] The Fastbus Intersegment Processor (FIP) is a 32-bit microprocessor based Fastbus Master serving as a node in multi-segment, multi-layer data acquisition systems. Its architecture allows independent, parallel processing at each node in the system, and supports asynchronous operation of each layer via Event buffering and message communication. An attached memory module, the Event Directory for Intersegment Processor, is a hardware-assisted multi-event buffer which maintains Event activity and history when used by independent source and sink masters. Their use in the Delphi TPC Data acquisition system is reviewed. (author). 2 figs
Source
Budinich, M.; Catelli, E.; Colavita, A. (eds.); International Centre for Theoretical Physics, Trieste (Italy); 346 p; ISBN 9971-50-742-0; 
; 1988; p. 284; World Scientific; Singapore (Singapore); International conference on the impact of digital microelectronics and microprocessors on particle physics; Trieste (Italy); 28-30 Mar 1988
; 1988; p. 284; World Scientific; Singapore (Singapore); International conference on the impact of digital microelectronics and microprocessors on particle physics; Trieste (Italy); 28-30 Mar 1988