[en] A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor (CMOS) devices is investigated. Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile. First, a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate. Then different BCl₃-based plasmas are applied to etch the TaN metal gate and find that BCl₃/Cl₂/O₂/Ar plasma is a suitable choice to get a vertical TaN profile. Moreover, considering that Cl₂ almost has no selectivity to Si substrate, BCl₃/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl₃/Cl₂/O₂/Ar plasma. Finally, we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies. (semiconductor technology)