[en] The Run IIa CDF Silicon Upgrade has recently finished installation. The detector uses revision D of the SVX3 readout IC. This final revision incorporated new features in order to improve the potential of dead-timeless operation. This paper describes measurements of dead-timeless effects on silicon strip readout on the test bench. This paper also describes tests of the dynamic pedestal subtraction circuitry, which is shown to improve greatly the dead-timeless performance of the silicon systems

[en] A search for the lepton-flavour violating decay D⁰ →e^±μ^∓ is made with a dataset corresponding to an integrated luminosity of 3.0 fb^-1 of proton–proton collisions at centre-of-mass energies of 7 TeV and 8 TeV, collected by the LHCb experiment. Candidate D⁰ mesons are selected using the decay D^*+ → D⁰π⁺ and the D⁰ →e^±μ^∓ branching fraction is measured using the decay mode D⁰ → K^-π⁺ as a normalization channel. No significant excess of D⁰→e^±μ^∓ candidates over the expected background is seen, and a limit is set on the branching fraction, B(D⁰→e^±μ^∓) < 1.3 × 10^-8, at 90% confidence level. This is an order of magnitude lower than the previous limit and it further constrains the parameter space in some leptoquark models and in supersymmetric models with R-parity violation.

[en] The intermediate silicon layers detector (ISL) was proposed as a part of the upgraded CDF detector at the RUN-II of the Tevatron mean value of pp collider at Fermilab, scheduled to start in year 2000. The ISL is a large-radius (20-30 cm) silicon tracker with a total active area of about 3.5 m^. Located in the region between the silicon vertex detector and the central outer tracker, the ISL will allow tracking int he forward region and significantly improve it in the central area. Together with the SVX II the ISL forms a standalone, 3D silicon tracker. The challenge is to build a low-cost device which provides precise 3 D tracking in a approximately equal to 2 m long area with a minimal amount of material for the supporting structure. The conceptual design and the status of the project are reviewed

[en] The CMS Silicon Strip Tracker (SST) will be equipped with 15000 silicon micro-strip detector modules covering a surface of 200 m². This paper details the SST layout and updates the status of construction. Progress in the fabrication of module components is detailed, with focus on the front-end hybrid and silicon sensor production. The assembly of over 2200 modules using industrial methods is described; the quality assurance protocols have resulted in modules of extremely high mechanical and electrical quality

[en] The Run IIa CDF Silicon Upgrade has recently finished installation. The detector uses revision D of the SVX3 readout IC. This final revision incorporated new features in order to improve the potential of dead-timeless operation. This paper describes measurements of dead-timeless effects on silicon strip readout on the test bench. This paper also describes tests of the dynamic pedestal subtraction circuitry, which is shown to improve greatly the dead-timeless performance of the silicon systems

[en] The design and performance of prototype single-sided modules with ABCN-25 front-end chips and 10x10 cm² Hamamatsu silicon strip sensors is presented. A low mass module assembly has been achieved by gluing a single-sided flex circuit, with read out chips, directly onto the sensor. The design exploits the embedded shunt regulation within the ABCN-25 providing for a distributed and scalable powered architecture. This allows for multiple modules to be linked together serially to form larger stave structures of up to 12 modules. The stave's digital I/O is realised as a multi-drop LVDS bus flex cable glued to the stave core assembly using a custom receiver/transmitter ASIC (BCC). The results of preliminary electrical tests with 4 module stavelets will be presented.

[en] We studied several devices with different distances of the sensitive region to the cut edge after severe hadron irradiation. They have been characterized in term of the bias voltage drop on the various guard ring (GR) structures and their charge collection performance. Current pixel detectors are made with n-type silicon with n-side readout. This geometry requires backplane processing for implanting GR structures on the backplane of the sensor. This increases the cost and the complexity of the device, but on the other hand offers GR structures on both sides, with possibly a more efficient reduction of the edge potential and beneficial effects on reducing the insensitive area. We present the comparison of n-in-p and n-in-n detectors with similar geometry to show the effect of the double GR structure before and after hadron irradiation.

[en] This work presents the first held at Liverpool University measurements of pixel sensors with n-type readout implant in the p-type bulk before and after irradiation of samples by 24 GeV protons to doses 7x10¹⁵ and 1.5x10¹⁶ protons/cm². A comparison is given for two measurement techniques; one based on the FE-I3 readout chip designed for the ATLAS and the other using the Beetle chip developed for the LHCb experiments at CERN.

[en] The electrical properties of hadron irradiated silicon detectors change over several years after irradiation. This annealing process has a strong dependence on temperature and it can be accelerated or decelerated by lowering or elevating the temperature at which the sensors are kept. This is exploited to investigate the long term behaviours of irradiated silicon detectors that are, or will be, installed in the experiment at the current and upgraded LHC at CERN. Elevated temperatures (up to 80°C) are used to accelerate the effect of annealing to study the expected changes of the sensor performances over several years of room temperature equivalent time. Low temperatures are applied to the sensors also when not operated to suppress undesired effects of annealing. The acceleration factors with respect to nominal room temperature (RT = 20°C) have been established monitoring the changes of the capacitance-voltage characteristics (CV) with time at various temperatures. In the experiments, the maximum high temperature envisaged out of operation cannot exceed much 20°C. It is important to measure the changes of the relevant parameters (charge collection reverse current, noise) at this temperature to verify the annealing behaviours in realistic conditions for planning the operation scenario (i.e. bias voltage and temperature during and outside operation) of the silicon sensors. We show here the study of room temperature annealing of the charge collection, reverse current and noise of silicon microstrip detectors after two doses of hadron irradiation (2 and 10 × 10¹⁵ n_eq cm⁻²) . These doses are chosen to represent the expected levels in the future upgrade of the LHC at CERN (High Luminosity LHC, HL-LHC) for the microstrip and pixel layers. The measurements show that a suitable choice of annealing time at 20°C can partially recover the degraded charge collection and reduce the reverse current after a given dose of hadron irradiation.

[en] The development at CERN of low noise DC-DC converters for the powering of front-end systems enables the implementation of efficient powering schemes for the physics experiments at the HL-LHC. Recent tests made on the ATLAS short strip tracker modules confirm the full electromagnetic compatibility of the DC-DC converter prototypes with front-end detectors. The integration of the converters in the trackers front-ends needs to address also the material budget constraints. The impact of the DC-DC converters onto the material budget of the ATLAS tracker modules is discussed and mass reduction techniques are explored, leading to a compromise between electromagnetic compatibility and mass. Low mass shield implementations and Aluminum core inductors are proposed. Also, the impact on emitted noise due to a size reduction of critical components is discussed. Finally, material reduction techniques are discussed at the board layout and manufacturing levels.