[en] We fabricate and investigate high-quality graphene devices with contactless, suspended top gates and demonstrate the formation of graphene pnp junctions with tunable polarity and doping levels. The device resistance displays distinct oscillations in the npn regime, arising from the Fabry-Perot interference of holes between the two pn interfaces. At high magnetic fields, we observe well-defined quantum Hall plateaus, which can be satisfactorily fit to theoretical calculations based on the aspect ratio of the device.

[en] Coupling high-quality suspended atomic membranes to specialized electrodes enables the investigation of many novel phenomena, such as spin or Cooper pair transport in these two-dimensional systems. However, many electrode materials are not stable in the acids that are used to dissolve underlying substrates. Here we present a versatile and powerful multilevel lithographical technique to suspend thin crystals, which can be applied to the vast majority of substrate, crystal and electrode materials. Using this technique, we fabricated suspended graphene devices with Al electrodes and a mobility of 5500 cm² V^-1 s^-1. We also demonstrate, for the first time, fabrication and measurement of a free-standing thin Bi₂Se₃ crystal, which has low contact resistance to electrodes and a mobility of ∼>580 cm² V^-1 s^-1.

[en] Heterostructure field-effect transistors (hetero-FETs) are experimentally demonstrated, consisting of van der Waals heterostructure channels based on a 2D semiconductor. By optimally selecting the band alignment of the heterostructure channels, different output characteristics of the hetero-FETs were achieved. In atomically thin WSe₂/MoS₂ hetero-FET with staggered energy band, the oscillating transfer characteristic and negative transconductance were realized. With near-broken-gap alignment in the MoTe₂/SnSe₂ heterostructure channel, a superior reverse-biased current was obtained in the hetero-FETs, which can be analyzed as typical tunneling current. Our study on the hetero-FET-based atomically thin van der Waals heterostructure channel, provides significant inspiration and reference to novel heterostructure FETs. (paper)

[en] Two-dimensional layered materials (2DLMs) have attracted broad interest from fundamental sciences to industrial applications. Their applications in memory devices have been demonstrated, yet much still remains to explore optimal materials and device structure for practical application. In this work, a forming-free, bipolar resistive switching behavior are demonstrated in 2D TiO₂-based resistive random access memory (RRAM). Physical adsorption method is adopted to achieve high quality, continuous 2D TiO₂ network efficiently. The 2D TiO₂ RRAM devices exhibit superior properties such as fast switching capability (20 ns of erase operation) and extremely low erase energy consumption (0.16 fJ). Furthermore, the resistive switching mechanism is attributed to the formation and rupture of oxygen vacancies-based percolation path in 2D TiO₂ crystals. Our results pave the way for the implementation of high performance 2DLMs-based RRAM in the next generation non-volatile memory (NVM) application. (paper)

[en] Two-dimensional layered materials (2DLMs) are radically different from conventional bulk semiconductors, and major challenges in achieving practical 2DLM devices with good performance lie in the areas of improving the electrical contacts that connect 2DLMS with electrodes rather than in improving the quality of the channel material itself. To meet this challenge, we have devised a promising large-scale synthesis method for few-layer MoS₂ film integrated with unique fabrication process that provides good contact. A thin layer of Mo was first deposited using sputtering evaporation and defined by a shadow mask, instead of immediate sulfurization in a chemical vapor deposition (CVD) furnace. Au contact electrodes were then deposited on Mo, followed by further sulfurization, which readily provides source-drain electrodes for synthesized MoS₂. Top-gated transistors based on such MoS₂ film show improved device performance compared to transistors fabricated using the traditional method. The transfer line method was further applied to verify that the proposed method could effectively decrease the contact resistance by more than 10 times, which can be attributed to the incomplete sulfurization of Mo atoms beneath the Au electrodes. It is envisioned that the proposed method could eventually be used to provide uniform and low contact resistance for CVD-grown 2DLM devices. (paper)

[en] A spin-coating method was applied to obtain thinner and smoother PEO/LiClO₄ polymer electrolyte films (EFs) with a lower level of crystallization than those obtained using a drop-casting method. When the applied frequency was as high as 10 kHz, the specific capacitance of such EFs with thicknesses of 1.5 μm was on the order of 1 μF∙cm⁻², a value larger than most of the previously reported results achieved from the same material. We then combined the thin EFs with two-dimensional (2D) materials to fabricate a MoS₂ transistor with a top gate right above the channel, defined by a shadow-mask method, and an inverter device. This transistor showed excellent static characteristics and the inverter device showed excellent switching performance at 100 Hz, which indicates a fast polarization response of the thin EFs. Such device architecture is suitable for future low power and flexible electronics based on 2D materials. .

[en] In the past fifty years, complementary metal-oxide-semiconductor integrated circuits have undergone significant development, but Moore’s law will soon come to an end. In order to break through the physical limit of Moore’s law, 2D materials have been widely used in many electronic devices because of their high mobility and excellent mechanical flexibility. And the emergence of a negative capacitance field-effect transistor (NCFET) could not only break the thermal limit of conventional devices, but reduce the operating voltage and power consumption. This paper demonstrates a 2D NCFET that treats molybdenum disulfide as a channel material and organic P(VDF-TrFE) as a gate dielectric directly. This represents a new attempt to prepare NCFETs and produce flexible electronic devices. It exhibits a 10^6 on-/off-current ratio. And the minimum subthreshold swing (SS) of the 21 mV/decade and average SS of the 44 mV/decade in four orders of magnitude of drain current can also be observed at room temperature of 300 K. (paper)

[en] Chemical vapor deposition synthesis of semiconducting transition metal dichalcogenides (TMDs) offers a new route to build next-generation semiconductor devices. But realization of continuous and uniform multilayer (ML) TMD films is still limited by their specific growth kinetics, such as the competition between surface and interfacial energy. In this work, a layer-by-layer vacuum stacking transfer method is applied to obtain uniform and non-destructive ML-MoS₂ films. Back-gated field effect transistor (FET) arrays of 1L- and 2L-MoS₂ are fabricated on the same wafer, and their electrical performances are compared. We observe a significant increase of field-effect mobility for 2L-MoS₂ FETs, up to 32.5 cm² V⁻¹ s⁻¹, which is seven times higher than that of 1L-MoS₂ (4.5 cm² V⁻¹ s⁻¹). Then we also fabricated 1L-, 2L-, 3L-, and 4L-MoS₂ FETs to further investigate the thickness-dependent characteristics of transferred ML-MoS₂. Measurement results show a higher mobility but a smaller current on/off ratio as the layer number increases, suggesting that a balance between mobility and current on/off ratio can be achieved in 2L- and 3L-MoS₂ FETs. Dual-gated structure is also investigated to demonstrate an improved electrostatic control of the ML-MoS₂ channel. (paper)

[en] Semiconductive two dimensional (2D) materials have attracted significant research attention due to their rich band structures and promising potential for next-generation electrical devices. In this work, we investigate the MoS₂ field-effect transistors (FETs) with a dual-gated (DG) architecture, which consists of symmetrical thickness for back gate (BG) and top gate (TG) dielectric. The thickness-dependent charge transport in our DG-MoS₂ device is revealed by a four-terminal electrical measurement which excludes the contact influence, and the TCAD simulation is also applied to explain the experimental data. Our results indicate that the impact of quantum confinement effect plays an important role in the charge transport in the MoS₂ channel, as it confines charge carriers in the center of the channel, which reduces the scattering and boosts the mobility compared to the single gating case. Furthermore, temperature-dependent transfer curves reveal that multi-layer MoS₂ DG-FET is in the phonon-limited transport regime, while single layer MoS₂ shows typical Coulomb impurity limited regime. (paper)

[en] 2D semiconductors have emerged as candidates for next-generation electronics. However, previously reported 2D transistors which typically employ the gate-first process to fabricate a back-gate (BG) configuration while neglecting the thorough impact on the dielectric capping layer, are severely constrained in large-scale manufacturing and compatibility with complementary metal-oxide-semiconductor (CMOS) technology. In this study, dual-gate (DG) field-effect transistors have been realized based on wafer-scale monolayer MoS${}_2$ and the gate-last processing, which avoids the transfer process and utilizes an optimized top-gate (TG) dielectric stack, rendering it highly compatible with CMOS technology. Subsequently, the physical mechanism of TG dielectric deposition and the corresponding controllable threshold voltage (V${}_{TH}$) shift is investigated. Then the fabricated TG-devices with a large on/off ratio up to 1.7 × 10${}^9$, negligible hysteresis (≈14 mV), and favorable stability. Additionally, encapsulated TG structured photodetectors have been demonstrated which exhibit photo responsivity (R) up to 9.39 × 10${}^3$ A W${}^{-<!--\; ???\; -->1}$ and detectivity (D*) ≈2.13 × 10${}^{13}$ Jones. The result paves the way for future CMOS-compatible integration of 2D semiconductors for complex multifunctional IC applications. (© 2024 Wiley‐VCH GmbH)