[en] To investigate the mechanism by which Sb at the SiO_2/SiC interface improves the channel mobility of 4H-SiC MOSFETs, 1 MHz capacitance measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements were performed on Sb-implanted 4H-SiC MOS capacitors. The measurements reveal a significant concentration of Sb donors near the SiO_2/SiC interface. Two Sb donor related CCDLTS peaks corresponding to shallow energy levels in SiC were observed close to the SiO_2/SiC interface. Furthermore, CCDLTS measurements show that the same type of near-interface traps found in conventional dry oxide or NO-annealed capacitors are present in the Sb implanted samples. These are O1 traps, suggested to be carbon dimers substituted for O dimers in SiO_2, and O2 traps, suggested to be interstitial Si in SiO_2. However, electron trapping is reduced by a factor of ∼2 in Sb-implanted samples compared with samples with no Sb, primarily at energy levels within 0.2 eV of the SiC conduction band edge. This trap passivation effect is relatively small compared with the Sb-induced counter-doping effect on the MOSFET channel surface, which results in improved channel transport.

[en] Engineered or ‘virtual’ substrates are of interest to extend the range of epitaxially-grown semiconductor heterostructures available for device applications. To this end, elastically strain-relaxed square features up to 30 µm in size and having an in-plane lattice constant as much as 0.49% larger than the lattice constant of GaAs were fabricated from MOCVD-grown GaAs/In_0.08Ga_0.92As/GaAs heterostructures by the in-place bonding method, using either AlAs or Al_0.7Ga_0.3As as the sacrificial layer. TEM images show that the solution-bonded interface is flat with a network of sessile edge dislocations that accommodates the different in-plane lattice constants of the feature and the GaAs substrate and a small rotation of the bonded features. Micro-Raman spectroscopy, which has a spatial resolution of ∼1 µm, was shown to be useful for characterizing lattice mismatch strain ≥ 0.0023, i.e. with an order of magnitude lower sensitivity than high-resolution XRD. (paper)

[en] Deep level defects in n-type GaAs_1−xBi_x having 0 < x < 0.012 and GaAs grown by molecular beam epitaxy (MBE) at substrate temperatures between 300 and 400 °C have been investigated by Deep Level Capacitance Spectroscopy. Incorporating Bi suppresses the formation of an electron trap with activation energy 0.40 eV, thus reducing the total trap concentration in dilute GaAsBi layers by more than a factor of 20 compared to GaAs grown under the same conditions. We find that the dominant traps in dilute GaAsBi layers are defect complexes involving As_Ga, as expected for MBE growth at these temperatures.

[en] Deep level transient spectroscopy (DLTS) measurements were performed on p–i–n diodes having i-regions that include a GaAs_1−xBi_x layer sandwiched between two GaAs layers, all grown at T < 400 °C. A GaAs_1−xBi_x/GaAs heterostructure with Bi fraction x = 4.7% grown at 285 °C was found to have several traps in concentrations of ∼5 × 10¹⁵ cm⁻³. The location of the observed traps in the i-region is determined from simulations of the band diagrams of these devices at the bias conditions used for the DLTS measurements and confirmed by DLTS spectra taken at various filling voltages

[en] Capacitance-voltage (C-V) and Deep-Level-Transient Spectroscopy (DLTS) measurements were performed on Metal-Oxide-Semiconductor (MOS) capacitors fabricated on 4H-SiC with the SiO₂ layer grown by Sodium-Enhanced Oxidation. This technique has yielded 4H-SiC MOS transistors with record channel mobility, although with poor bias stability. The effects of the mobile positive charge on the C-V characteristics and DLTS spectra were investigated by applying a sequence of positive and negative bias-temperature stresses, which drifted the sodium ions toward and away from the SiO₂/4H-SiC interface, respectively. Analytical modeling of the C-V curves shows that the drift of sodium ions in the SiO₂ layer during the voltage sweep can explain the temperature dependence of the C-V curves. The effects of lateral fluctuations of the surface potential (due to a non-uniform charge distribution) on the inversion layer mobility of MOS transistors are discussed within a two-dimensional percolation model