No abstract available

[en] Single event upset (SEU) effect in semiconductor devices and integrated circuits (IC) was simulated using Geant4. General structure and simulation method were established to study SEU effect accurately. Ionization and nuclear reaction mechanisms were used to generate statistical profiles of charge deposition in sensitive volume of semiconductor devices and ICs. The results showed that the device structure with a tungsten layer above the sensitive volume could be more likely to cause an SEU. (authors)

[en] Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction. (semiconductor devices)

[en] Nano-scale Hf/HfO_2-based resistive random-access-memory (RRAM) devices were fabricated. The cross-over between top and bottom electrodes of RRAM forms the metal–insulator–metal sandwich structure. The electrical responses of RRAM are studied in detail, including forming process, SET process and RESET process. The correlations between SET voltage and RESET voltage, high resistance state and low resistance state are discussed. The electrical characteristics of RRAM are in a strong relationship with the compliance current in the SET process. The conduction mechanism of nano-scale Hf/HfO_2-based RRAM can be explained by the quantum point contact model. (paper)

[en] The performance of a partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DT-MOS) is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOI DTMOSFET structure (drain/source-on-local-insulator structure) is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.

[en] Based on the platform of 0.35 μm PDSOI CMOS process technology, the partially depleted silicon-on-insulator dynamic threshold voltage (PDSOI DT) NMOS with an H-gate was implemented. The analog characteristics and RF characteristics of the gate-body contacted dynamic threshold voltage H-gate NMOS and conventional H-gate NMOS were performed and compared. Furthermore, the fundamental operation principle and physical mechanism of the PDSOI H-gate DTMOS compared with the conventional H-gate NMOS are analyzed in detail. The results indicate that the cutoff frequency can reach 40 GHz and the maximum oscillation frequency 29.43 GHz as V_gs = 0.7 V and V_ds = 1 V (semiconductor devices)

[en] A bimodal effect of transconductance was observed in narrow channel PDSOI sub-micron H-gate PMOSFETs, which was accompanied with the degeneration of device performance. This paper presents a study of the transconductance bimodal effect based on the manufacturing process and electrical properties of those devices. It is shown that this effect is caused by a diffusion of donor impurities from the N⁺ region of body contact to the P⁺ poly gate at the neck of the H-gate, which would change the work function differences of the polysilicon gate and substrate. This means that the threshold voltage of the device is different in the width direction, which means that there are parasitic transistors paralleled with the main transistor at the neck of the H-gate. The subsequent devices were fabricated with layout optimization, and it is demonstrated that the bimodal transconductance can be eliminated by mask modification with N⁺ implantation more than 0.2 μm away from a poly gate. (semiconductor devices)

[en] Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35 μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE. (semiconductor devices)

[en] In most of the total dose radiation models, the drift of the threshold voltage and the degradation of the carrier mobility were only studied when the bulk potential is zero. However, the measured data indicate that the total dose effect is closely related to the bulk potential. In order to model the influence of the bulk potential on the total dose effect, we proposed a macro model. The change of the threshold voltage, carrier mobility and leakage current with different bulk potentials were all modeled in this model, and the model is well verified by the measured data based on the 0.35 μm PDSOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences, especially the part of the leakage current. (semiconductor devices)

[en] Thin gate oxide radio frequency (RF) PDSOI nMOSFETs that are suitable for integration with 0.1 μm SOI CMOS technology are fabricated, and the total ionizing dose radiation responses of the nMOSFETs having four different device structures are characterized and compared for an equivalent gamma dose up to 1 Mrad (Si), using the front and back gate threshold voltages, off-state leakage, transconductance and output characteristics to assess direct current (DC) performance. Moreover, the frequency response of these devices under total ionizing dose radiation is presented, such as small-signal current gain and maximum available/stable gain. The results indicate that all the RF PDSOI nMOSFETs show significant degradation in both DC and RF characteristics after radiation, in particular to the float body nMOS. By comparison with the gate backside body contact (GBBC) structure and the body tied to source (BTS) contact structure, the low barrier body contact (LBBC) structure is more effective and excellent in the hardness of total ionizing dose radiation although there are some sacrifices in drive current, switching speed and high frequency response.