[en] We studied organic resistive memory devices with interfacial oxide layers, the thickness of which depended on O₂ plasma treatment time. The different interfacial oxide thicknesses sequentially changed the ON and OFF states of the final memory devices. We found that the memory devices that had undergone additional plasma treatment showed higher ON/OFF ratios than devices without the treatment, which was due to the relatively large OFF resistance values. However, a long oxidation process widened the threshold voltage distribution and degraded the switching reproducibility. This indicates that the oxidation process should be carefully optimized to provide practical high-performance organic memory.

[en] The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 μm² to 200 x 200 nm². From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I_ON/I_OFF∼10⁴), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10 000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

[en] We fabricated an array-type organic nonvolatile memory device with multilayer graphene (MLG) film embedded in polyimide (PI) layers. The memory devices showed a high ON/OFF ratio (over 10⁶) and a long retention time (over 10⁴ s). The switching of the Al/PI/MLG/PI/Al memory devices was due to the presence of the MLG film inserted into the PI layers. The double-log current–voltage characteristics could be explained by the space-charge-limited current conduction based on a charge-trap model. A conductive atomic force microscopy found that the conduction paths in the low-resistance ON state were distributed in a highly localized area, which was associated with a carbon-rich filamentary switching mechanism. (paper)

[en] We fabricated and characterized a large number of octanedithiol (denoted as DC8) molecular devices as vertical metal-molecule-metal structure with or without using an intermediate conducting polymer layer of poly (3,4-ethylenedioxythiophene) stabilized with poly(4-styenesulfonic acid) (called as PEDOT:PSS). The electronic transport properties of DC8 molecular devices with and without PEDOT:PSS layer were statistically compared in terms of current density and device yield. The yields of the working molecular devices were found to be ∼ 1.75% (84 out of 4800 devices) for Au/DC8/Au junctions and ∼ 58% (74 out of 128 devices) for Au-DC8/PEDOT:PSS/Au junctions. The tunneling decay constants were obtained with the Simmons tunneling model and a multibarrier tunneling model for two kinds of molecular devices with and without PEDOT:PSS layer.

[en] In this study, we demonstrate a transistor-type ZnO nanowire (NW) memory device based on the surface defect states of a rough ZnO NW, which is obtained by introducing facile H₂O₂ solution treatment. The surface defect states of the ZnO NW are validated by photoluminescence characterisation. A memory device based on the rough ZnO NW exhibits clearly separated bi-stable states (ON and OFF states). A significant current fluctuation does not exist during repetitive endurance cycling test. Stable memory retention characteristics are also achieved at a high temperature of 85 °C and at room temperature. The surface-treated ZnO NW device also exhibits dynamically well-responsive pulse switching under a sequential pulse test configuration, thereby indicating its potential practical memory applications. The simple chemical treatment strategy can be widely used for modulating the surface states of diverse low-dimensional materials. (paper)

[en] A technique for directly growing two-dimensional (2D) materials onto conventional semiconductor substrates, enabling high-throughput and large-area capability, is required to realise competitive 2D transition metal dichalcogenide devices. A reactive sputtering method based on H₂S gas molecules and sequential in situ post-annealing treatment in the same chamber was proposed to compensate for the relatively deficient sulfur atoms in the sputtering of MoS₂ and then applied to a 2D MoS₂/p-Si heterojunction photodevice. X-ray photoelectron, Raman, and UV–visible spectroscopy analysis of the as-deposited Ar/H₂S MoS₂ film were performed, indicating that the stoichiometry and quality of the as-deposited MoS₂ can be further improved compared with the Ar-only MoS₂ sputtering method. For example, Ar/H₂S MoS₂ photodiode has lower defect densities than that of Ar MoS₂. We also determined that the factors affecting photodetector performance can be optimised in the 8–12 nm deposited thickness range. (paper)

[en] Artificial synapses based on 2D MoS${}_2$ memtransistors have recently attracted considerable attention as a promising device architecture for complex neuromorphic systems. However, previous memtransistor devices occasionally cause uncontrollable analog switching and unreliable synaptic plasticity due to random variations in the field-induced defect migration. Herein, a highly reliable 2D MoS${}_2$/Nb${}_2$O${}_5$ heterostructure memtransistor device is demonstrated, in which the Nb${}_2$O${}_5$ interlayer thickness is a critical material parameter to induce and tune analog switching characteristics of the 2D MoS${}_2$. Ultraviolet photoelectron spectroscopy and photoluminescence analyses reveal that the Schottky barrier height at the 2D channel-electrode junction of the MoS${}_2$/Nb${}_2$O${}_5$ heterostructure films is increased, leading to more effective contact barrier modulation and allowing more reliable resistive switching. The 2D/oxide memtransistors attain dual-terminal (drain and gate) stimulated heterosynaptic plasticity and highly precise multi-states. In addition, the memtransistor devices show an extremely low power consumption of ≈6 pJ and reliable potentiation/depression endurance characteristics over 2000 pulses. A high pattern recognition accuracy of ≈94.2% is finally achieved from the synaptic plasticity modulated by the drain pulse configuration using an image pattern recognition simulation. Thus, the novel 2D/oxide memtransistor makes a potential neuromorphic circuitry more flexible and energy-efficient, promoting the development of more advanced neuromorphic systems. (© 2021 Wiley‐VCH GmbH)

[en] Highlights: • Fabrication of heterojunctions by stacking n-type MoS₂ film on a p-type Ge epilayer. • Temperature-dependent current-voltage characteristics of the MoS₂/p-type Ge device. • The charge transport mechanism in three regimes. • The thermionic emission is dominant in the high-temperature regime. • The trap-assisted tunneling mechanism is dominant in the low-temperature regime. Significant effort has been devoted to constructing two-dimensional transition metal dichalcogenides-based hybrid heterojunctions with enhanced performance or unique functionalities for versatile device applications in emerging electronics and optoelectronics. In this study, we report the temperature-dependent electronic charge transport characteristics in MoS₂/p-type Ge heterojunction diodes. From the current-voltage (I-V) characteristics of the heterojunction device, it is observed that different transport phenomena can occur depending upon the temperature and bias voltage. The charge transport is dominated by thermionic emission in the high-temperature regime above 300 K, whereas in low-temperature regime below 300 K, the charge transport mechanism transitions from the thermionic emission to the tunneling mechanism associated with trap sites. In particular, the I-V characteristics in the low-temperature regime show a transition from the direct tunneling at a low bias to the Fowler-Nordheim tunneling mechanism at a high bias. This could be well described by the electrical analyses on temperature-dependent I-V behavior and corresponding energy band diagrams.

[en] Scalable sub-micrometer molybdenum disulfide (${\mathrm{M}\mathrm{o}\mathrm{S}}_2$) flake films with highly uniform coverage were created using a systematic approach. An electrohydrodynamic (EHD) printing process realized a remarkably uniform distribution of exfoliated ${\mathrm{M}\mathrm{o}\mathrm{S}}_2$ flakes on desired substrates. In combination with a fast evaporating dispersion medium and an optimal choice of operating parameters, the EHD printing can produce a film rapidly on a substrate without excessive agglomeration or cluster formation, which can be problems in previously reported liquid-based continuous film methods. The printing of exfoliated ${\mathrm{M}\mathrm{o}\mathrm{S}}_2$ flakes enabled the fabrication of a gas sensor with high performance and reproducibility for ${\mathrm{N}\mathrm{O}}_2$ and ${\mathrm{N}\mathrm{H}}_3$. (paper)

[en] Although insertion of a thin insulating layer between metal electrodes and a semiconducting channel is an effective way to improve device performance, the exact reason for improvement in performance is not elucidated. Herein, the role of an Al${}_2$O${}_3$ interlayer sandwiched between Al metal electrodes and an amorphous indium-gallium-zinc-oxide semiconducting channel is systematically investigated. The Al${}_2$O${}_3$ interlayer results in not only a good transistor performance with increased on current but also improved gate bias stress stability. The improvement is primarily attributed to a doping effect and mitigation of interface defects. Energy-band diagrams, experimentally obtained from temperature-variable electrical characterization and electrostatic force microscopy, validate the channel doping effect, which increase the tunneling probability of the electron charge carriers via a reduction of the Schottky barrier width. A comprehensive study on the influence of various processing parameters, including Al${}_2$O${}_3$ thickness, post-annealing treatment conditions, and types of electrodes, on the transistor device is also performed. This approach guides the practical implementation of stable sol-gel oxide-based thin-film transistors and promotes integrated circuitry applications. (© 2021 Wiley-VCH GmbH)