[en] The electrical transients induced by EMP exhibit unique characteristics which differ considerably from transients associated with other phenomena such as lightning, switching, and circuit malfunctions. The suppression techniques developed to handle more common transients, though not necessarily the same devices, can be used for EMP damage protection. The suppression devices used for circuit level EMP protection are referred to as Terminal Protection Devices (TPD). Little detailed data describing the response of TPD's to EMP-related transients have been published. While most vendors publish specifications for TPD performance, there is little standardization of parameters and TPD response models are not available. This lack of parameter standardization has resulted in a proliferation of test data that is sometimes conflicting and often not directly comparable. This paper derives and/or defines a consistent set of parameters based on EMP circuit hardening requirements and on measurable component parameters and is concerned only with use of TPD's to prevent permanent damage. Three sets of parameters pertaining to pertinent TPD functional characteristics were defined as follows: standby parameters, protection parameters, and failure parameters. These parameters are used to evaluate a representative sample of TPD's and the results are presented in matrix form to facilitate the selection of devices for specific hardening problems

[en] This paper summarizes the results of a major test program which involved the measurement of the pulse power failure thresholds of 41 integrated circuit types, representing seven logic families. The pulse widths used in these tests range from 0.1 microsecond to 10 microseconds. The failure threshold data have been grouped by logic family and test terminal to form failure categories. A simple failure model has been developed which is useful in predicting the failure thresholds of untested devices

[en] This paper presents the results of an investigation of quantitative procedures for assessing the probability of failure (P/sub F/) of tactical military systems exposed to a neutron radiation environment. All assessments are made with a 90 percent confidence in the determined probability of failure. Two analytical models are developed for predicting the probability of failure of transistor circuits based on small quantity test data or manufacturer's specifications of gain (β) and gain bandwidth product (f/sub T/). The formulation of these models incorporates the influence of circuit design margins. For circuits where the failure fluence is determined by a single device, a nomograph is presented for calculating P/sub F/ as a function of f/sub T/, initial gain, fluence, and the circuit design margin. Examples are also provided for the use of the models for determining P/sub F/ via Monte Carlo analyses for circuits including several transistors

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