[en] IT Department of Synchrotron SOLEIL is structured along of a team of software developers responsible for the development and maintenance of all software from hardware controls up to supervision applications. With a very heterogonous development environment such as, several software languages, strongly coupled components and an increasing number of releases of the entire software stacks, it has become mandatory to standardize the entire development process through a “Continuous Delivery approach”; making it easy to release and deploy on time at any time. We achieved our objectives by building up a Continuous Delivery solution around two aspects, Deployment Pipeline and DevOps. A deployment pipeline is achievable by extensively automating all stages of the delivery process (the continuous integration of software, the binaries build and the integration tests). Another key point of Continuous Delivery is also a close collaboration between software developers and system administrators, often known as the DevOps movement. This paper details the feedbacks on how we have adopted this Continuous Delivery approach, modifying our daily development team life and give an overview of the future steps. (author)

[en] Time resolved experiments are one of the major services that synchrotrons can provide to scientists. The short, high frequency and regular flashes of synchrotron light are a fantastic tool to study the evolution of phenomena over time. To carry out time resolved experiments, beamlines need to synchronize their devices with these flashes of light with a jitter shorter than the pulse duration. For that purpose, Synchrotron SOLEIL has developed the TimBeL (Timing Beamlines) board fully interfaced to TANGO framework. The TimBeL system is a compact PCI board. It is made of a mother with one daughter board. All functions are performed inside a FPGA (Field Programmable Gate Array) implemented on the mother board. A PLX Technology chip is used to communicate with the compact PCI crate. To enable experiments to remain always synchronous with the same bunch of electrons, the storage ring clock (CLK-SR) and the radio frequency clock (CLK-RF) are provided by the machine to beamlines. These clocks are used inside the FPGA as main clocks for state machines. Because the jitter is too large on the FPGA outputs, a daughter board with a jitter cleaner has been added to the system. This board also provides delay lines for compensating time offsets by 10 ps steps. This paper presents the main features required by time resolved experiments and how we achieved our goals with the TimBeL board

[en] Attenuators are commonly used on beamlines to control incident photon flux. Attenuators are mainly controlled by software. In some experimental cases using various diffraction techniques, this architecture is not fast enough to manage high flux variation. The fast attenuation system inserts and extracts filters quickly, allowing very fast beam attenuation at the maximum rate allowed by the filter mechanism and the beam detector response. To build the solution, we used an off-the-shelf CPCI General Purpose board (GPIO) from TEWS that is based on a SPARTAN-3 Xilinx FPGA: We have developed a daughter board and an embedded VHDL program. The logic is dedicated to maintaining incident detector photon flux within an acceptable range for optimized measurements and protecting the X ray detector against over-exposure. This system is part of a continuous scan process. Some low level process logic is also embedded in order to optimize data exchange. During continuous scanning, this process allows each experimental data item collected to be associated with its corresponding photon flux value. This system is in operation on the SIXS beamline and will be soon installed on the DIFFABS beamline. This paper describes the principle and the results obtained with this solution and the possible improvements and perspectives (interfacing more complex detectors such as XPad).

[en] An increasing number of synchrotron beamlines need to use several detection techniques in parallel and in fast acquisition modes. It means measuring signals from all detectors 'on-the-fly' while actuators are moving in order to avoid significant time overheads that are introduced by motor settling times in step-scan mode. The large amount of data produced in such experiment has to be managed. Relying on our Tango based software distributed architecture, a set of C++/java libraries, Tango devices and GUI (graphical user interface) applications has been developed to form a 'distributed fast acquisition system for multi-detector experiments' (FLYSCAN) for the future Soleil beamline Nanoscopium. This paper presents the status of the development and the implementation of FLYSCAN