[en] Gate oxides for SiC lateral MOSFETs have been formed in N2O by rapid thermal processing (RTP) as an alternative to the conventional furnace process. This innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to a standard oxidation, but also to produce oxide layers with quality comparable to the one grown in a conventional furnace. Moreover, a significant improvement of the oxide quality and MOSFET performance is observed when performing in-situ a H2 anneal prior to oxidation as surface pretreatment. The channel mobility and the breakdown field of the gate oxide are considerably increased. (author)

[en] Al recoil implantation have been shown to be a possible alternative to direct Al ion implantation to avoid usual problems linked with Al sources. Poor efficiency of the recoil + annealing process is observed if no barrier or an oxyde screen layers are used. This problem can be solved using a Si₃N₄ screen layer. Then, P-N and N⁺/P/N structures can be obtained with deep low doped P-well with reduced thermal budget

[en] A new electronic stopping power model for Monte Carlo simulation of ion implantation into 6H-SiC is presented. This model is based on the nonlinear density functional approach of Echenique et al. for the energy loss of slow ions moving through an electron gas and the ab initio pseudopotential calculations of Park et al. for the map of valence electrons of 6H-SiC crystal. A modified linear response theory has been used to treat the core electrons stopping. This model does not need fitting parameters and allows to fit the experimental distributions of implanted dopants in SiC both the peak region and the channeling tail of the SIMS profiles

[en] We report the results of an ab initio study of N and P dopants in SiC. We find that while N substitutes most favorably at a C lattice site, P does so preferably at a Si site, except in n-doping and Si-rich 3C-SiC. Furthermore, we consider a series of dopant complexes that could form in high-dose implantation, in order to investigate the dopant activation behavior in this limit. We find that all N complexes considered lead to passivation through the formation of a deep level. For P, the most stable aggregate is still an active dopant, while passivation is only observed for complexes with a higher formation energy. We discuss how these results could help in the understanding of the observed experimental high-dose doping and codoping behavior of these species

[en] We review some of the electric properties of self-organized graphene monolayers on the carbon face of SiC. From sparse surface defects acting as nucleation centres, isolated graphene layers grow in the shape of triangles or ribbons on the step bunched SiC surface. Using e-beam lithography, standard Hall bars have been made. At low magnetic fields, conductance fluctuations, weak localization, electron–electron interactions are usually observed. At higher magnetic fields, the anomalous quantum Hall (QHE) effect typical of monolayer graphene is also observed. In this regime, the breakdown of the QHE appears at moderate currents, which we attribute to the persistence of impurities in the vicinity of the graphene layer. Moderate heating (150 °C) is not sufficient to overcome this issue, and moreover, the carrier concentration cannot be controlled. In order to control the carrier concentration, bottom-gated samples are also presented. In these devices, the carrier concentration can be modulated, but the breakdown current remains very small. (paper)

[en] We present a method of selective epitaxial growth of few layers graphene (FLG) on a ''prepatterned'' silicon carbide (SiC) substrate. The methods involves, successively, the sputtering of a thin aluminium nitride (AlN) layer on top of a monocrystalline SiC substrate and, then, patterning it with e-beam lithography and wet etching. The sublimation of few atomic layers of Si from the SiC substrate occurs only through the selectively etched AlN layer. The presence of the Raman G-band at ∼1582 cm^-1 in the AlN-free areas is used to validate the concept. It gives absolute evidence of selective FLG growth

No abstract available

[en] 4H-SiC PIN diodes have been fabricated on a Norstel P⁺/N/N⁺ substrate with a combination of Mesa and JTE as edge termination. A breakdown voltage of 4.5 kV has been measured at 1 µA for devices with an active area of 2.6 mm². The differential on-resistance at 15 A (600 A cm⁻²) was of only 1.7 mΩ cm² (25 °C) and 1.9 mΩ cm² at 300 °C. The reduced recovery charge was of 300 nC for a switched current of 15 A (500 V) at 300 °C. 20% of the diodes showed no degradation at all after 60 h of dc stress (25–225 °C). Other 30% of the diodes exhibit a reduced voltage shift below 1 V. For those diodes, the leakage current remains unaffected after the dc stress. Electroluminescence investigations reveal a very low density of stacking faults after the dc stress. The manufacturing yield evidences the efficiency of the substrate surface preparation and our technological process

[en] In this paper, the impact of temperature and time stress on gate oxide stability of several multi-implanted and epitaxied 4H-SiC nMOSFET is presented. The oxide layer was processed under a rapid thermal process (RTP) furnace. The variation of the main electrical parameters is shown. We report the high quality and stability of such implanted MOSFETs, and point out the very low roughness effect of the on-axis-cut sample. Particularly, in the best case, effective channel mobility ( μ _fe) overcomes 20 cm².V⁻¹.s⁻¹ at 300 °C for a channel length of 12 μ m, which is very encouraging for implantation technology. Starting from 200 °C, the apparent increase of the μ _fe peak of the MOSFET ceases and tends to saturate with further temperature increase. This is an indication of the potential of MOSFETs built on on-axis substrates. Thus, starting from the real case of an implanted MOSFET, the global purpose is to show that the electrical performance of such an on-axis-built device can tend to reach that of the ideal case, i.e. epitaxied MOSFET, and even overcome its electrical limitation, e.g. in terms of threshold voltage stability at high temperature. (paper)

[en] A comparative study of the electrical characteristics of 3.3 kV SiC Schottky barrier (SBD), junction bipolar Schottky (JBS) and PiN diodes is presented. 3.3 kV class 4H-SiC SBD, JBS and PiN diodes have been fabricated with an analogous technology process on similar epi wafers. Diodes have been characterized in forward, reverse and switching mode in the 25 °C–300 °C temperature range. The optimum performance of the diodes depends on the adequate use of the unipolar or bipolar advantages and is established by the final application specifications. In this respect, a reverse recovery charge versus on-resistance diagram for different current densities is also presented. DC stress tests have been performed to investigate the forward voltage drift, related to the formation of stacking faults, during the bipolar mode of operation