[en] Developing a tens of picosecond sensor which will survive the radiation environment of the future high physics experiments is a challenge. For position detection, sensors in the HV-CMOS 150 nm process technology have proven to be inherently rad-hard thanks to the full depletion of several hundred microns of the substrate. A first iteration of a timing sensor in this technology, named CACTUS, has been tested with encouraging results but with a time resolution far from the 60 ps expected from the simulations due to unforeseen capacitance. A new prototype called MiniCACTUS has been designed and submitted to fabrication in order to address this issue. It includes integrated front-end electronics with discrimination for each pixel, a programmable slow-control, internal DACs and bias circuits. The baseline pixel pitches are 1 mm² and 0.5 mm² with additional test structures sizing 50 µm x 50 µm and 50 µm x 150 µm. The prototypes received from the foundry have been thinned to 100 µm and 200 µm and were post processed for backside polarization. The 200 µm samples have shown a breakdown voltage higher than 300 V, a S/N better than 50 with cosmic rays, and a timing resolution around 80 ps, limited by the resolution of our timing reference system. A test-beam campaign is foreseen at CERN this year in order to assess precisely the timing resolution of the sensor. All these results will be presented at the conference.

[en] Monolithic CMOS active pixel sensors in depleted substrates (DMAPS) are an attractive development for pixel tracker systems in high-rate collider experiments. The radiation tolerance of these devices is enhanced through technology add-ons and careful design, which allow them to be biased with large voltages and collect charge through drift in highly resistive silicon bulks. In addition, the use of commercial CMOS technology would reduce the current production complexity and costs of large module areas. The LF-Monopix chips are two fully functional large-scale DMAPS prototypes with a column drain readout architecture. They were designed in a 150 nm CMOS process that made it possible to place and isolate each pixel’s front-end circuitry within a charge collection electrode of a size comparable to the pixel area. This contribution will give an overview of the chips' design, sensor and front-end performance with a focus on radiation hardness. Measurements on neutron irradiated samples showed an in-time detection efficiency of ∼97% after a NIEL dose of 1×1015neq/cm2. Moreover, the gain did not degrade and noise only increased by 25% after a X-ray Total Ionizing Dose of 100 Mrad. The characterization of the latest prototype has also shown a positive outcome from the effort to implement a matrix with a column length of 2 centimeters and a reduced pixel pitch of 150×50 um2.