[en] Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e"- (rms) at zero farad for a power consumption of 8 mW per channel. The linearity error is lower than 1% and the overall gain of the readout channel is 165 V/pC. The crosstalk between the channels is less than 3%. By connecting the readout ASIC to a CdZnTe detector, we obtained a γ-ray spectrum, the energy resolution is 5.1% at the 59.5-keV line of "2"4"1Am source. (authors)

[en] CMOS pixel sensors (CPS) are attractive candidates for charged particle tracking in high energy physics experiments. However, CPS chips fabricated with standard CMOS processes, especially the built-in SRAM IP cores, are not radiation hard enough for this application. This paper presents a radiation hard SRAM for improving the CPS radiation tolerance. The SRAM cell is hardened by increasing the static noise margin (SNM) and adding P+ guard rings in layout. The peripheral circuitry is designed by building a radiation-hardened logic library. The SRAM internal timing control is hardened by a self-adaptive timing design. Finally, the SRAM design was implemented and tested in the Austriamicrosystems (AMS) 0.35 μm standard CMOS process. The prototype chips are adapted to work with frequencies up to 80 MHz, power supply voltages from 2.9 V to 3.3 V and temperatures from 0 °C to 60 °C. The single event latchup (SEL) tolerance is improved from 5.2 MeV cm²/mg to above 56 MeV cm²/mg. The total ionizing dose (TID) tolerance is enhanced by the P+ guard rings and the self-adaptive timing design. The single event upset (SEU) effects are also alleviated due to the high SNM SRAM cell and the P+ guard rings. In the near future, the presented SRAM will be integrated in the CPS chips for the STAR experiments.

[en] CMOS active pixel sensors (APS) suffer from serious dark-current degradation when they are exposed in radiation environment. Considering the general situation that there are multiple kinds of energetic particles in radiation environment, a dark-current estimation method for pixel sensors due to mixed radiation particles is proposed in this paper. Based on the radiation effects induced by particles of all kinds, the dark-current amplitudes distribution among the pixels can be predicted through probabilistic analysis. Validation is implemented upon the radiation dark-image data of CMOS APS devices, which shows that the predicted dark-current distribution matches very well with the experimental data, and the difference is no more than 15%.

[en] This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e"− (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

[en] This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

[en] The monolithic active pixel sensor (MAPS) is a promising choice to track charged particles in high energy physics experiments, such as the solenoidal tracker at RHIC (STAR). In order to achieve a clean reference voltage and simplify the cable placement, a full on-chip reference generator is presented in this paper. By utilizing a buffer and a series RC network, the proposed circuit can achieve good stability, low power and low noise, without any external components. The output voltage is adjustable to compensate the influence of the fabrication process. The generator has been implemented and fabricated in a standard 0.35 μm CMOS process. Its silicon area is 327 μm×119 μm. The total power dissipation is 677 μW at a supply voltage of 3.3 V. The measured results show that only 5.84% of the total noise in MAPS is induced by the proposed reference generator. The comparison with the other optional circuit based on a current buffer is also presented.

[en] The presented work is dedicated to designing a readout ASIC used in CdZnTe-based gamma-ray spectrometers for radionuclide identification. In order to achieve high linearity in a large dynamic range, an active resistor is utilized. Since the active resistor induces high noise, a $\mathrm{CR}-\mathrm{(RC)}$ ${}^2$ slow shaper with two different stages is proposed to suppress the noise. The integrating resistors in the first stage are implemented by transistors operating in triode region, while the active resistor is utilized in the second stage. A prototype chip with eight channels has been designed and fabricated in a standard commercial 1P6M 0.18 $\mathrm{\mu }$m CMOS process. The measured nonlinear error is less than 1% with the input charge ranging from $-1.4$ fC to $-56$ fC, owning to the proposed slow shaper. Measured ENC is about 180 $e^{-}$ at input capacitance of 0 F with a slope of 7.7 $e^{-}$/pF.

[en] This paper presents a 4-channel avalanche photodiode readout ASIC for the electromagnetic calorimeter in the 2–7 GeV high intensity electron positron accelerator. A large detector capacitance of the avalanche photodiode will increase equivalent noise charge and extend rise time of the front-end preamplifier, resulting in attenuated energy and time resolution of the ASIC. A low-noise preamplifier and a 5th-order high-linearity shaper were proposed to decrease the noise induced by a 270 pF detector capacitance. The ASIC is fabricated using a standard 0.18-$\mathrm{\mu }$m CMOS technology, and the die size of the prototype chip is 1.1 mm $\times$ 2.4 mm. The input charge range of the ASIC is from 4.8 fC to 400 fC. The event rate of the ASIC can achieve 400k count/s. Nonlinear error of the shaper is less than 2%. The measured signal to noise ratio is better than 7.8 at a shaping time of 800 ns. The timing resolution of the ASIC is better than 300 ps at an input charge of 100 fC.