[en] The NA48 transceiver consists of a pole-zero compensation from 150 ns down to 10 ns and a differential line driver which delivers up to ± 1.5 V into 50 Ω. A circuit, using surface mounted components, has been realized and has equipped the 15,000 channels of the liquid Krypton calorimeter since summer 1996; it is described along with its performances. (author)

[en] Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32-channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto-trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range [0-100] photo-electrons. In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance

[en] SKIROC (Silicon Kalorimeter Integrated ReadOut Chip) is the front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) at the future International Linear Collider. The fine granularity of the ILC calorimeters implies an extremely large number of electronics channels (82 millions) which is a new feature of ''imaging'' calorimetry. Moreover, for compactness, the chips must be embedded inside the detector without any external component making essential the reduction of the power consumption to 25 μWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time).

[en] PARISROC is the front-end ASIC designed to read 16 photomultiplier (PM) tubes for neutrino experiments. It's able to shape, discriminate, convert and readout data in an autonomous and channel-independent mode. The tests made on PARISROC1 have shown some limitations on time measurements and on hit rate capability. In order to correct these points, the digital part of PARISROC2 has been completely modified to add new features and improvements. First, it integrates a new time to amplitude converter with less than 1 ns resolution. Secondly, conversion and readout has been speeded-up by a factor of 4 to handle the PM hit rate. The chip was received in February 2010.

[en] CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

[en] The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

[en] Imaging calorimetry depends heavily on the development of high performance, highly integrated readout ASICs embedded inside the detector which readout the millions of foreseen channels. Suitable ASICs prototypes have been fabricated in 2006-2007 and show good preliminary performance.

[en] PARISROC is a complete readout chip, in AMS SiGe 0.35 μm technology, for photomultipliers array. It is a front-end electronics ASIC which allows trigerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R and D program, funded by French National Agency for Research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerless acquisition and only sends out the relevant data by network to the central data storage. This data management reduces considerably the cost of these detectors. This paper describes the front-end electronics ASIC called PARISROC which integrates totally independents 16 channels with a variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.

[en] HARDROC is the front end chip designed to read out the Resistive Plate Chambers foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the calorimeter implies thousands of electronics channels per cubic meter which is a new feature of 'imaging' calorimetry. Moreover, for compactness, chips must be embedded inside the detector making crucial the reduction of the power consumption down to 12 μ W per channel. This is achieved using power-pulsing and online zero-suppression. Around 800 HARDROC3 were produced in 2015. The overall performance and production tests will be detailed.

[en] Imaging calorimetry at the International Linear Collider requires highly granular and innovative detectors. Technological prototypes have been built and tested under the CALICE collaboration framework and FP6 EUDET, FP7 AIDA European programs. These prototypes are readout by multi-channel chips named SKIROC2, SPIROC2 and HARDROC2, designed by the IN2P3 OMEGA group in AMS SiGe 350 nm technology. In this presentation, the ASIC architectures and test results on test bench and at system level will be described as well as first results of test bench measurements performed on HARDROC3, which is the first of the ''3rd generation'' chip to be submitted and where the 64 channels are handled independently to perform zero suppress on chip