[en] A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

[en] The Fastbus Intersegment Processor (FIP) is a Fastbus processor based on a MOTOROLA MC68020 microprocessor system. It will be used in several detectors of the Delphi LEP experiment at CERN. Its architecture is oriented towards cellular multi-layered acquisition systems, where it provides data collection, processing and buffering at a particular level, as well as control and synchronisation from one level to the next. The Fastbus architecture, Fastbus interfaces, and the application foreseen for the Delphi TPC are covered in detail in the paper

[en] The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

[en] A fast hardware processor for straight line finding MWPCs has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described. (orig.)

[en] This paper discusses HEP experiments in the next decade which will require sophisticated trigger systems in which massively parallel processing structures such as the Associative String Processor (ASP) could take an important part. For such systems, ultimate real time performance may be achieved in a matched network of high performance (computation and communication oriented) conventional processors, using ASPs for data searching and filtering. Requirements and specifications for an ASP Embedded Node (ASPEN) are defined, and the application of a prototype ASPEN architecture to medium term trigger applications is reviewed. Larger applications which could integrate such nodes for local and/or global data processing are then presented

[en] In France the research in nuclear physics is made in 2 institutes: IN2P3 (National Institute for Nuclear Physics and Particle Physics) that belongs to CNRS (National Center for Scientific Research) and IRFU (Institute of Research of the Fundamental laws of the Universe) that belongs to CEA (French Alternative Energies and Atomic Energy Commission). This series of slides describes the organization, the activities and the main research programs of both institutes

No abstract available

[en] The NA48 charged trigger is a mixed hardware and software real-time processing system intended to detect the interesting configurations of K⁰ charged decays. It achieves real-time event building, track reconstruction and kinematics computation on drift chamber data at an event rate of 100 kHz and within a maximum decision latency of 100 μs. The system uses data driven, FPGA-based coordinate builders, a hardware event builder based on a crossbar switch, and a farm of up to 16 event processors for its software part. It has been installed and operated at CERN since 1995. After a description of the constraints and architecture of the various subsystems, the paper gives an account of the results and performance of the system based on the 1996/1997 runs. More specifically, the replacement of the present DSP-based implementation of the processing farm by RISC processors will be discussed. (author)

[en] The Fastbus Intersegment Processor (FIP) is a 32-bit microprocessor based Fastbus Master serving as a node in multi-segment, multi-layer data acquisition systems. Its architecture allows independent, parallel processing at each node in the system, and supports asynchronous operation of each layer via Event buffering and message communication. An attached memory module, the Event Directory for Intersegment Processor, is a hardware-assisted multi-event buffer which maintains Event activity and history when used by independent source and sink masters. Their use in the Delphi TPC Data acquisition system is reviewed. (author). 2 figs

[en] This issue is dedicated to the 20. anniversary of the creation of the IRFU institute that gathers the research activities of CEA on physics. About 20 short articles present in a very pedagogical manner the various contributions of IRFU to the understanding of modern physics, it concerns neutrinos, dark matter, matter/anti-matter asymmetry, nucleon sub-structure, nuclear structure and the structure of the universe