[en] The NA48 transceiver consists of a pole-zero compensation from 150 ns down to 10 ns and a differential line driver which delivers up to ± 1.5 V into 50 Ω. A circuit, using surface mounted components, has been realized and has equipped the 15,000 channels of the liquid Krypton calorimeter since summer 1996; it is described along with its performances. (author)

[en] The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

[en] SKIROC (Silicon Kalorimeter Integrated ReadOut Chip) is the front end chip designed for the readout of the Silicon PIN diodes foreseen for the Electromagnetic CALorimeter (ECAL) at the future International Linear Collider. The fine granularity of the ILC calorimeters implies an extremely large number of electronics channels (82 millions) which is a new feature of ''imaging'' calorimetry. Moreover, for compactness, the chips must be embedded inside the detector without any external component making essential the reduction of the power consumption to 25 μWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time).

[en] CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

[en] For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 10⁶. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

[en] Imaging calorimetry depends heavily on the development of high performance, highly integrated readout ASICs embedded inside the detector which readout the millions of foreseen channels. Suitable ASICs prototypes have been fabricated in 2006-2007 and show good preliminary performance.

[en] HARDROC is the front end chip designed to read out the Resistive Plate Chambers foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the calorimeter implies thousands of electronics channels per cubic meter which is a new feature of 'imaging' calorimetry. Moreover, for compactness, chips must be embedded inside the detector making crucial the reduction of the power consumption down to 12 μ W per channel. This is achieved using power-pulsing and online zero-suppression. Around 800 HARDROC3 were produced in 2015. The overall performance and production tests will be detailed.

[en] Imaging calorimetry at the International Linear Collider requires highly granular and innovative detectors. Technological prototypes have been built and tested under the CALICE collaboration framework and FP6 EUDET, FP7 AIDA European programs. These prototypes are readout by multi-channel chips named SKIROC2, SPIROC2 and HARDROC2, designed by the IN2P3 OMEGA group in AMS SiGe 350 nm technology. In this presentation, the ASIC architectures and test results on test bench and at system level will be described as well as first results of test bench measurements performed on HARDROC3, which is the first of the ''3rd generation'' chip to be submitted and where the 64 channels are handled independently to perform zero suppress on chip

[en] Warm preamplifiers connected to a detector through 8 m cables have been evaluated in the frame of the RD3 accordion LAr calorimeter. The noise performance on workbench and on testbeam are presented and discussed. For fast calorimetry and for a particular range of detector capacitance, the warm preamplifiers are competitive with cold ones. (orig.)

[en] Power-pulsed readout potentially offers a solution to the problem of high power consumption of the electronics for detectors at the future International Linear Collider (ILC) experiments. A 33 × 50cm² Glass Resistive Plate Chamber (GRPC) equipped with a power-pulsed electronics board offering 1cm² lateral segmentation was successfully tested in a 3-Tesla magnet. A significant reduction in power consumption with no deterioration of the detector performance was obtained when the power-pulsing mode was applied. This result shows that highly granular calorimeters for ILC experiments are not only an attractive but also a realistic option.