[en] Low-bandgap semiconductors, such as InAs and InSb, are widely considered to be ideal for use in tunnel field-effect transistors to ensure sufficient on-current boosting at low voltages. This work elucidates the physical and mathematical considerations of applying conventional band-to-band tunneling models in low-bandgap semiconductors, and presents a new analytical alternative for practical use. The high-bandgap tunneling generates most at maximum field region with shortest tunnel path, whereas the low-bandgap generations occur dispersedly because of narrow tunnel barrier. The local electrical field associated with tunneling-electron numbers dominates in low-bandgap materials. This work proposes decoupled electric-field terms in the pre-exponential factor and exponential function of generation-rate expressions. Without fitting, the analytical results and approximated forms exhibit great agreements with the sophisticated forms both in high- and low-bandgap semiconductors. Neither nonlocal nor local field is appropriate to be used in numerical simulations for predicting the tunneling generations in a variety of low- and high-bandgap semiconductors

[en] This study elucidates the coupling of Schottky barriers and trapped charges involved in the source-side electrons programming and two-bit/cell reading of the Schottky barrier charge-trapping cells. Two-dimensional numerical iterations were employed to examine the distribution of electron injections and trapped charges, and to discuss the differences of physical mechanisms between the Schottky barrier and conventional cells. In the Schottky barrier cells, both the conduction and injection of electron carriers depend on the Schottky source barrier lowering. The source-side trapped charges alter the source-side lateral field distribution, reducing the maximum of the lateral electric field, and moving the subsequent injections away from the source edge. The distribution of total trapped-charges is considerably wider than that of the initial injection. However, because of source-side conduction, the excellent screening of second-bit effect is beneficial to operate the NOR-type multibit/cell charge-trapping memories. (paper)

[en] Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on–off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices. (paper)

[en] This paper presents a new, physical threshold voltage model to solve the ambiguity in determining the threshold voltage of double-gate (DG) MOSFETs. To avoid the difficulties of the conventional 2ψ_B model in nearly undoped DG MOSFETs, this study proposes to define the on–off switching based on the actual roles of the drift and diffusion components in the total drain current. The drift current strongly enhances beyond the threshold voltage, while the diffusion current plays a major role in the subthreshold. The threshold voltage is defined as the drift component that exceeds the diffusion counterpart. From the solutions of Poisson's equation, the drift and diffusion currents of DG MOSFETs are separately formulated to derive the analytical expressions of the threshold voltage and associated threshold current. This model provides a comprehensive description of the switching behavior of DG MOSFET devices, and offers a physical onset threshold current to determine the threshold voltage in practical extraction

[en] An insulated dielectric oxide (IDO) is presented for the dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to suppress the unwanted on- and off-state leakage currents in short-channel DS-SBMOS. The effects of the IDO on DS-SBMOS are investigated using two-dimensional device simulations. Although the dopant segregation technique can efficiently modify a Schottky barrier to improve Schottky barrier MOSFETs, the performance of scaled DS-SBMOS suffers from degraded short-channel behavior and ambipolar conduction from the extension of a heavily doped segregation layer. With sidewall IDO insulators between the heavily doped N+ segregation layer and P+ halo region, band-to-band and ambipolar leakage currents are simultaneously minimized. Thus, an optimal halo can be utilized to control the short-channel effect without any constraints in problematic leakage currents. Using the IDO architecture, DS-SBMOS can be successfully scaled as a promising candidate for next-generation CMOS devices

[en] This work thoroughly explores the considerations and optimizations of dopant segregated Schottky barrier MOSFETs (DS-SBMOS) using two-dimensional device simulations. The dependences of the device characteristics on the dopant segregated layer are clarified in the DS-SBMOS. The heavier and wider dopant segregation layer efficiently modifies the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, DS-SBMOS devices have slightly worse short-channel effects than conventional MOSFETs, because of additional segregation extensions into the silicon substrate. Importantly, apparent degradations of DS-SBMOS in ambipolar conduction are observed when a thinner gate-insulator or a heavier halo profile is used for the scaled short-channel DS-SBMOS. Dual workfunction gate (DWG) architecture is first proposed to optimize DS-SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal design of DS-SBMOS devices can be achieved using the DWG structure with enhanced driving current, minimized ambipolar conduction and a suitable short-channel effect as the gate-insulator is scaled down

[en] This work presents a novel Schottky barrier flash cell with promising source-side injection programming. The effects of the Schottky barrier on source-side injection programming are demonstrated by two-dimensional device simulations. The unique Schottky barrier at the source/channel interface significantly promotes the amount of source-side hot electrons to provide high injection efficiency at considerably low voltages without compromising between gate and drain biases. The new source-side injection Schottky barrier flash cell, which has a compact floating-gate structure with a metallic source/drain, is proposed for the first time as future flash memory

[en] This study elucidates the latent noise mechanisms in Schottky barrier MOSFETs (SBMOS; MOSFET: metal–oxide–semiconductor field effect transistor). The complex noise problems in SBMOS arise from the particular ambipolar current conduction and the additional interface states at metallic source/drain junctions. In addition to the excess noise of conventional MOSFETs, which is associated with gate oxide traps and variations in channel mobility, the interface traps at the metallic source/drain are key to the overall noise characteristics of SBMOS. Most possible noise sources under various operating conditions are summarized herein to provide a comprehensive understanding of how noise potentially limits the practical applications of SBMOS devices