[en] We report on the technology and growth optimization of GaAs/InAs core/shell nanowires. The GaAs nanowire cores were grown selectively by metal organic vapor phase epitaxy (SA-MOVPE) on SiO₂ masked GaAs ( 1-bar 1-bar 1-bar )B templates. These were structured by a complete thermal nanoimprint lithography process, which is presented in detail. The influence of the subsequent InAs shell growth temperature on the shell morphology and crystal structure was investigated by scanning and transmission electron microscopy in order to obtain the desired homogeneous and uniform InAs overgrowth. At the optimal growth temperature, the InAs shell adopted the morphology and crystal structure of the underlying GaAs core and was perfectly uniform. (paper)

[en] We investigated the suitability of lanthanum lutetium oxide (LaLuO₃) as a gate dielectric by fabricating InAs nanowire field-effect transistors. The LaLuO₃ layer was deposited by employing pulsed laser deposition. On transistors with a 1.6 µm long gate, a maximum transconductance of 11 µS at a source–drain bias voltage of 0.5 V was measured, while the threshold voltage had a value of −4.5 V. Owing to the complete coverage of the InAs nanowire by the LuLuO₃ layer no significant leakage current was found. On a transistor with a 240 nm long gate short-channel effects were observed. The transfer characteristics showed a hysteretic behavior, which is attributed to charging of states at the InAs/LaLuO₃ interface. We found that the threshold voltage gets reduced considerably when the temperature was decreased to 25 K. At this temperature the hysteresis in the transfer characteristics showed no dependence on the sweep rate

[en] The bottom-up assembly of semiconductor nanowires holds promise for future nanoelectronic devices. The high room temperature carrier mobility and the narrow direct bandgap make InAs an eligible material for this application. However, as recently reported, the conductivity of InAs nanowires could be influenced detrimentally by crystal defects such as twin planes and stacking faults. In this contribution, we report on different strategies to affect the nanowire crystallographic structure. Growth is performed by selective area MOVPE on partially masked substrates. The influence of growth rate, substrate orientation and Si doping on morphological, structural and electrical properties was investigated by scanning and transmission electron microscopy and two-and four-terminal measurements. It is found that especially the growth rate reduces the stacking fault density. Furthermore we observe an increase of conductivity and a decrease of nanowire aspect ratio with higher doping concentration. A correlation between doping, growth rate and electrical characteristics will be presented.

[en] We investigated the properties of gadolinium scandate (GdScO₃) as a gate dielectric for top-gate electrodes on undoped InAs nanowires. It is demonstrated that due to the high dielectric constant of GdScO₃ (k=22), a better control of the conductance of the nanowire is achieved compared to a reference SiO₂-isolated back-gate electrode. We analyzed the output and transfer characteristics of top-gate-controlled InAs wires at room temperature and at temperatures down to 4 K. Owing to the good coverage of the InAs nanowire by the 50-nm-thick GdScO₃ layer, which was deposited by pulsed-laser deposition, the gate leakage current is sufficiently suppressed. (orig.)