[en] This front-gate, back-gate, and sidewall response of SIMOX and ZMR MOS transistors to 10-keV x-ray and Co-60 irradiation is compared for SOI devices with and without hardened sidewall passivation. 14 refs., 4 figs

[en] The effects of total-dose radiation have been investigated for sidewall-hardened n-channel MOS transistors fabricated in zone-melt recrystallized (ZMR) and oxygen-implanted SOI films. Subthreshold leakage currents and threshold voltage shifts remained acceptably low for the superior ZMR devices at doses greater than 1 Mrad (SiO₂)

[en] We report measurements of the kinetics of tungsten metallization of porous silicon layers for the formation of buried conductors under single crystal silicon. The kinetics depend markedly on the partial pressure of the source gas and on the degree of porosity, in agreement with a proposed model in which the rate-limiting step is diffusion of WF₆ source gas through the narrow pore channels. Preliminary results are presented of the full isolation of silicon islands by buried metal

[en] The top-gate, back-gate, and sidewall response of SIMOX and ZMR SOI/MOS transistors to 10 keV x-ray and Co-60 irradiation is compared. For top-gate and sidewall insulators, Co-60 and 10-keV x-ray irradiations at matched dose rates lead to nearly identical response. Back-gate response, on the other hand, depends strongly on radiation energy and buried insulator thickness. Differences are observed of up to 60 percent for SIMOX (0.4 μm buried oxide), and up to 300 percent for ZMR (2.0 μm buried oxide), with Co-60 leading to increased response. Different x-ray to Co-60 correlation factors may be observed for other technologies with different sidewall and buried insulator materials and thicknesses. The authors demonstrate that it is not possible to define a generic set of worst-case radiation bias conditions for all SOI technologies. For these devices, it is shown that back-gate radiation response can be a strong function of transistor drain bias during exposure

[en] A prime motivating factor to develop silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) integrated circuit (IC) technologies is their increased impurity to transient radiation and single-event upset, as well as total immunity to ''latchup.'' However, SOI ICs are at least as sensitive to total-dose ionizing radiation as bulk ICs. Therefore, to ensure that the desired total-dose radiation hardness is properly designed and built into SOI MOS devices, it is important to develop reliable quick-turnaround, total-dose radiation screens for SOI transistors and circuits. Defining such a screen involves characterizing the unique response of SOI devices to different radiation sources, dose rates, and radiation and test bias conditions. In this summary the authors focus on what radiation source(s) should be used for evaluation of SOI process lot radiation hardness. The de facto standard for radiation hardness assurance testing is exposure of packaged parts to Co-60 gamma radiation. Lately, it has been suggested that a 10-keV x-ray source could be used to irradiate devices at the wafer level. This technique has practical advantages over Co-60 irradiations. Because irradiations are performed at the wafer level, information can be gained immediately after fabrication without the added delay and expense involved in packaging devices. In this summary, the authors compare x-ray and Co-60 irradiations of SIMOX and ZMR SOI MOS transistors. Front gate, sidewall, and backgate responses are examined. These results should facilitate material and process optimization efforts to improve the hardness of SOI devices

[en] Ion irradiation was used to pattern a region of red-light emitting porous silicon by eliminating visible-light photoluminescence (PL). The PL peak wavelength is approximately 735 nm and shows little dependence on the excitation-light wavelength. The ratio of PL intensities for different excitation wavelengths was shown to be proportional to the ratio of the absorption coefficients. Below saturation, the integrated PL intensity increased linearly with excitation-light power density

[en] It has been well established in recent years that silicon can be converted into highly porous material under the appropriate anodic etching conditions. Metallization of such a porous skeleton could be technologically interesting for device applications, especially if the resistance of the metal path could be made sufficiently low. The authors report results on the feasibility of forming buried conductors under single crystal silicon using low pressure chemical vapor deposition of tungsten on the internal surfaces of porous silicon. The infiltration of tungsten into the silicon depends on its porosity, and on tungsten deposition process parameters such as deposition duration, total deposition pressure, and carrier gas species. The resulting tungsten/porous silicon layers were characterized by transmission and scanning electron microscopy, by Rutherford backscattering and X-ray diffraction and by four-point probe resistivity measurements

[en] Total dose radiation effects were measured for sidewall-hardened n-channel SOI/MOS transistors, fabricated in zone-melt-recrystallized (ZMR) and oxygen-implanted (SIMOX) SOI materials. The authors compare the radiation responses of transistors with three types of sidewall or edge configurations: island transistors with passivated edges, island transistors without passivated edges, and edgeless (enclosed-gate) transistors. Data from these three test devices allow clear separation of front-, back-, and edge-channel conduction. Passivated edge channels were hard to Co-60 doses in excess of 24 Mrad(Si). The overall hardness of the passivated-edge transistors is limited only by the radiation-induced threshold voltage shifts (about -1 V at 1.0 Mrad) of the top channel. No significant differences in total-dose response of ZMR and SIMOX devices were observed under the radiation conditions employed

[en] The authors have performed a study to determine whether silicon very-large-scale integrated circuits (VLSICs) can survive the high temperature (up to 300⁰C) and total-dose radiation environments (up to 10 Mrad over a 7-10 year system life) projected for a very-high-power space nuclear reactor platform. It is shown that circuits built on bulk epitaxial silicon cannot meet the temperature requirement because of excessive junction leakage currents. However, circuits built on silicon-on-insulator (SOI) material can meet both the radiation and temperature requirements. From a study of interface-trap generation and annealing, they find that one cannot depend on the elevated temperatures of a space nuclear power platform to automatically improve MOS total-dose radiation hardness. Still, at high-enough temperatures (above 175⁰C for these devices) and long enough times postirradiation, device response can be essentially independent of total dose. Reliability and performance issues are also discussed. They find that the temperature dependence of the threshold voltage of the SOI transistors is less than that of bulk transistors. Moreover, the ''zero-temperature coefficient'' current is much smaller for these ''floating-body'' SOI devices (-- 4 μA) than for bulk devices (-- 60 μA). Survivability of high-temperature SOI VLSICs in space, including immunity to transient and single-event upset (SEU), is also addressed. While a large number of practical issues remain to be resolved, no fundamental barrier against the successful development of VLSICs on SOI for use in very-high-power space nuclear reactor systems has been identified

[en] Chemical vapor deposition (CVD) metallization of the internal surfaces of porous silicon could result in technically interesting device applications if the resistance of the metal path could be made sufficiently low. The authors report on the characteristics of subsurface tungsten conductors deposited by CVD on the internal surfaces of anodically prepared porous silicon. Because the WF-6/Si reduction reaction displaces a greater volume of silicon than is replaced by the resulting metal layer, silicon pores are actually enlarged by the reaction, permitting WF-6 gas to penetrate deeply into the porous structure without blocking the passages. The structure thus forms an attractive test bed for the investigation of diffusion and flow characteristics of refractory metal source gases in a high aspect ratio configuration