[en] This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In_0.6Ga_0.4As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption

[en] The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band

[en] Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k·p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model

[en] Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In_0.53Ga_0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In_0.53Ga_0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET

[en] Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60 mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60 mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In_0.53Ga_0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60 mV/dec SS, with an on-current comparable to the conventional source design

[en] Heterostructure tunnel field-effect transistors (HTFET) are promising candidates for low-power applications in future technology nodes, as they are predicted to offer high on-currents, combined with a sub-60 mV/dec subthreshold swing. However, the effects of important quantum mechanical phenomena like size confinement at the heterojunction are not well understood, due to the theoretical and computational difficulties in modeling realistic heterostructures. We therefore present a ballistic quantum transport formalism, combining a novel envelope function approach for semiconductor heterostructures with the multiband quantum transmitting boundary method, which we extend to 2D potentials. We demonstrate an implementation of a 2-band version of the formalism and apply it to study confinement in realistic heterostructure diodes and p-n-i-n HTFETs. For the diodes, both transmission probabilities and current densities are found to decrease with stronger confinement. For the p-n-i-n HTFETs, the improved gate control is found to counteract the deterioration due to confinement

[en] Group IV based tunnel field-effect transistors generally show lower on-current than III-V based devices because of the weaker phonon-assisted tunneling transitions in the group IV indirect bandgap materials. Direct tunneling in Ge, however, can be enhanced by strain engineering. In this work, we use a 30-band k · p method to calculate the band structure of biaxial tensile strained Ge and then extract the bandgaps and effective masses at Γ and L symmetry points in k-space, from which the parameters for the direct and indirect band-to-band tunneling (BTBT) models are determined. While transitions from the heavy and light hole valence bands to the conduction band edge at the L point are always bridged by phonon scattering, we highlight a new finding that only the light-hole-like valence band is strongly coupling to the conduction band at the Γ point even in the presence of strain based on the 30-band k · p analysis. By utilizing a Technology Computer Aided Design simulator equipped with the calculated band-to-band tunneling BTBT models, the electrical characteristics of tensile strained Ge point and line tunneling devices are self-consistently computed considering multiple dynamic nonlocal tunnel paths. The influence of field-induced quantum confinement on the tunneling onset is included. Our simulation predicts that an on-current up to 160 (260) μA/μm can be achieved along with on/off ratio > 10⁶ for V_DD = 0.5 V by the n-type (p-type) line tunneling device made of 2.5% biaxial tensile strained Ge

[en] Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In_0_._5_3Ga_0_._4_7As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET