[en] 2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS₂ field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS₂ FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS₂ flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS₂ interface, but also from the MoS₂-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO₂ substrate. Furthermore, we analyse MoS₂ FETs of different channel thickness on three different substrates, SiO₂, hBN and Al₂O₃, by correlating the p-branch I _ON/I _OFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al₂O₃ which enables us to observe ambipolar transport in a bilayer MoS₂ FET. These results highlight that MoS₂ is indeed an ambipolar material, and the absence of ambipolar transport in MoS₂ FETs is strongly correlated to its dielectric environment and processing conditions. (paper)

[en] The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band

[en] Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In_0.53Ga_0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In_0.53Ga_0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET

[en] Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60 mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60 mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In_0.53Ga_0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60 mV/dec SS, with an on-current comparable to the conventional source design

[en] Heterostructure tunnel field-effect transistors (HTFET) are promising candidates for low-power applications in future technology nodes, as they are predicted to offer high on-currents, combined with a sub-60 mV/dec subthreshold swing. However, the effects of important quantum mechanical phenomena like size confinement at the heterojunction are not well understood, due to the theoretical and computational difficulties in modeling realistic heterostructures. We therefore present a ballistic quantum transport formalism, combining a novel envelope function approach for semiconductor heterostructures with the multiband quantum transmitting boundary method, which we extend to 2D potentials. We demonstrate an implementation of a 2-band version of the formalism and apply it to study confinement in realistic heterostructure diodes and p-n-i-n HTFETs. For the diodes, both transmission probabilities and current densities are found to decrease with stronger confinement. For the p-n-i-n HTFETs, the improved gate control is found to counteract the deterioration due to confinement

[en] Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In_0_._5_3Ga_0_._4_7As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET