[en] A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

[en] We measured the switching time statistics for a TiO₂ memristor and found that they followed a lognormal distribution, which is a potentially serious problem for computer memory and data storage applications. We examined the underlying physical phenomena that determine the switching statistics and proposed a simple analytical model for the distribution based on the drift/diffusion equation and previously measured nonlinear drift behavior. We designed a closed-loop switching protocol that dramatically narrows the time distribution, which can significantly improve memory circuit performance and reliability.

[en] Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

[en] We report a direct-write method to form vertical metal-metal connections between crossing metal wires at a 60 nm pitch. Patterned connections within crossed wire arrays enable construction of nanoscale-to-microscale demultiplexer circuits which are required elements in any integrated nanowire memory, logic or sensing system. However, fabricating dense nano-micro connections below a pitch of ∼80 nm exceeds standard electron-beam (e-beam) lithography capabilities, and usually requires more than 10 yield-reducing process steps including two critical pitch overlay alignments. We describe direct-write programming that requires only two high-yield process steps and micron-scale overlay accuracy, and appears to be extendable to sub-30 nm pitch. Electron-beam irradiation was used to modify the electrical conductivity of a 23 nm insulating polymer film separating metal nanowires and microwires of a demultiplexer crossbar array. Junction conductivities were programmed over five orders of magnitude from G<10^-11 to G>10^-6 Ω^-1. Monte Carlo simulations of electron scattering assist optimization of structural design, electron energy and dose. The time, voltage and temperature dependences of programmed junctions indicate that the insulating polymer is graphitized into conductive fragments that show percolation-limited electronic transport

[en] We measured the real-time switching of metal–oxide memristors with sub-nanosecond resolution and recorded the evolution of the current and voltage during both ON (set) and OFF (reset) events. From these we determined the dynamical behavior of the conductivity for different applied bias amplitudes. Quantitative analysis of the energy cost and switching dynamics showed 115 fJ for ON-switching and 13 pJ for OFF-switching when resistance change was limited to 200%. Results are presented that show a favorable scaling with speed in terms of energy cost and reducing unnecessary damage to the devices.

[en] Ultradense memory and logic circuits fabricated at local densities exceeding 100 x 10⁹ cross-points per cm² have recently been demonstrated with nanowire crossbar arrays. Practical implementation of such nanocrossbar circuitry, however, requires effective demultiplexing to solve the problem of electrically addressing individual nanowires within an array. Importantly, such a demultiplexer (demux) must also be tolerant of the potentially high defect rates inherent to nanoscale circuit fabrication. We have built a 50 nm half-pitch nanocrossbar circuit using imprint lithography and configured it for a demux application. Utilizing a class of Hamming codes in the hardware design, we experimentally demonstrate defect-tolerant demux operations on a 12 x 8 nanocrossbar array with up to two stuck-open defects per addressed line

[en] We have studied the effect of top electrode materials on the switching behavior of TaO _x based memristors with an identical switching oxide layer and bottom electrode stack. We found that the virgin resistance, electroforming and switching performance depend heavily on the chemical property of the top electrode materials. In addition, the electrical properties of metal oxides formed with the top electrodes also contribute to the overall memristor performance, including the nonlinearity of the current–voltage relationship. These results provide insights into understanding of memristor behavior as well as approaches for device property engineering. (paper)

[en] We report sub-nanosecond switching of a metal–oxide–metal memristor utilizing a broadband 20 GHz experimental setup developed to observe fast switching dynamics. Set and reset operations were successfully performed in the tantalum oxide memristor using pulses with durations of 105 and 120 ps, respectively. Reproducibility of the sub-nanosecond switching was also confirmed as the device switched over consecutive cycles.

[en] We demonstrated a cost-effective and deterministic method of patterning 3D cone arrays over a large area by using nanoimprint lithography (NIL). Cones with tip radius of less than 10 nm were successfully duplicated onto the UV-curable imprint resist materials from the silicon cone templates. Such cone structures were shown to be a versatile platform for developing reliable, highly sensitive surface enhanced Raman spectroscopy (SERS) substrates. In contrast to the silicon nanocones, the SERS substrates based on the Au coated cones made by the NIL offered significant improvement of the SERS signal. A further improvement of the SERS signal was observed when the polymer cones were imprinted onto a reflective metallic mirror surface. A sub-zeptomole detection sensitivity for a model molecule, trans-1,2-bis(4-pyridyl)-ethylene (BPE), on the Au coated NIL cone surfaces was achieved.

[en] Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaO _x ) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10⁶ cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing. (paper)